GAL18V10B-15LJN - Brand New LATTICE IC Chips
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Description
The GAL18V10, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide a very flexible 20-pin PLD. CMOS circuitry allows the GAL18V10 to consume much less power when compared to its bipolar counterparts. The E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.
Specifications and features
• HIGH PERFORMANCE E2 CMOS TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 111 MHz
— 5.5 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS Advanced CMOS Technology
• LOW POWER CMOS
— 75 mA Typical Icc
• ACTIVE PULL-UPS ON ALL PINS
• E2CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Uses Standard 22V10 Macrocell Architecture
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATIONApplication Scenarios
The GAL18V10 is commonly used in DMA control, state machine control, high speed graphics processing, and standard logic speed upgrades. Its reconfigurable logic and reprogrammable cells make it suitable for complex logic designs.
Comparison
The GAL18V10 has the advantage of utilizing a high-performance CMOS process and E2 technology, which allows for fast reprogramming and low power consumption. It also offers a flexible 20-pin PLD with ten output logic macrocells. The disadvantage is that it may not be suitable for applications that require higher speeds than its maximum propagation delay of 7.5 ns.
Advantages- High-performance CMOS process
- E2 technology for fast reprogramming
- Low power consumption
- Flexible 20-pin PLD
- Ten output logic macrocells
Disadvantages- Not suitable for applications requiring speeds higher than 7.5 ns maximum propagation delay
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Similar parts: 430483 , Click to view
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Datasheet
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Popular parts of the same kind
- Datasheet: Download GAL18V10B-15LJN
- Chipdatas Part: CD87-GAL18V10B-15LJN
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/25 15:17 +0800
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- Full or Partial Refund , If the item is not as described
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