Description

These circuits are monolithic J-FET input operational amplifiers incorporating well matched, high voltage J-FET on the same chip with standard bipolar transistors. This amplifiers feature low input bias and offset currents, low input offset voltage and input offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection. The devices are also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise level.

Specifications and features

■ HIGH INPUT IMPEDANCE J-FET INPUT STAGE

■ HIGH SPEED J-FET OP-AMPs : up to 20MHz, 50V/µs

■ OFFSETVOLTAGEADJUSTMENT DOES NOT DEGRADE DRIFT OR COMMON-MODE REJECTION AS IN MOST OF MONOLITHIC AMPLIFIERS

■ INTERNAL COMPENSATION AND LARGE DIFFERENTIAL INPUTVOLTAGECAPABILITY (UP TO VCC+)

Application Scenarios

■ PRECISION HIGH SPEED INTEGRATORS

■ FAST D/A AND CONVERTERS

■ HIGH IMPEDANCE BUFFERS

■ WIDEBAND, LOW NOISE, LOW DRIFT AMPLIFIERS

■ LOGARITHMIC AMPLIFIERS

■ PHOTOCELL AMPLIFIERS

■ SAMPLE AND HOLD CIRCUITS