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Description
The PXB4010EV1.3G is an interworking element for 8 E1/T1 lines, serving as a gateway between ATM networks and timeslot based PDH networks. It is a member of Infineon's ATM chip set and is configurable to T1 or E1 mode via an external pin. With 8 T1/E1 ports, it can be independently configured to ATM or AAL mode. The PXB4010EV1.3G supports various features such as ATM cell mapping into PDH, B-ISDN User-Network interface, AAL1 adaptation, channel associated signaling support, echo canceller mode, partially filled cells, selectable sequence count algorithm, and more. It also features IMA interface, generic framer interfaces, UTOPIA industry standard interface, a 16-bit generic microprocessor interface, external synchronous SSRAM, build-in data path loops for test, and a P-BGA 256 package. The temperature range of the PXB4010EV1.3G is from -40° to +85°C.
Specifications and features
- Full duplex ATM Packetizer/Depacketizer for 8 E1/T1 highways
- Configurable to T1 or E1 mode via external pin
- 8 T1/E1 ports configurable independently to ATM or AAL Mode
- Various modes supported: ATM Mode (PXB 4219/4220/4221), AAL Mode (PXB 4220/4221)
- Support for B-ISDN User-Network interface, physical layer operation, and operation at different bit rates
- AAL1 adaptation with or without overhead
- T1/E1 unstructured and structured services
- Channel Associated Signaling (CAS) support
- Echo Canceller Mode
- Programmable filling thresholds for partially filled cells
- Selectable Sequence Count Algorithm
- Reassembly buffer with Cell Delay Variation compensation
- Clock recovery circuit using Synchronous Residual Time Stamp (SRTS) or Adaptive Clock Method (ACM)
- Trunk freezing and conditioning
- IMA interface with programmable threshold, output signals, and port number indication
- 8 generic framer interfaces with transmit clock selector support
- UTOPIA industry standard interface
- 16-bit generic microprocessor interface for control and configuration
- External synchronous Flow-Through SSRAM
- Data path loops for test
- 3.3 Volt power supply with 5 Volt tolerant inputs
- P-BGA 256 package
- Temperature range from -40° to +85°CApplication Scenarios
The PXB4010EV1.3G can be used as an interworking element in networks where ATM and PDH technologies need to be integrated. It can be deployed in various applications such as telecom networks, data centers, and other communication systems that require the conversion between ATM and PDH protocols.
Comparison
Advantages- Full duplex operation for 8 E1/T1 lines
- Configurable to T1 or E1 mode
- Independent configuration of 8 T1/E1 ports
- Support for various modes and protocols
- Flexible channel adaptation options
- Reliable clock recovery options
- Programmable filling thresholds for efficient cell handling
- Trunk freezing and conditioning capabilities
- Industry standard interfaces for easy integration
- Power efficient with low power dissipationDisadvantages- Optional patent fee for Synchronous Residual Time Stamp (SRTS) clock recovery
- Slightly higher power dissipation compared to some other models
- External synchronous SSRAM required for optimal performance
- Limited package options -
Similar parts: 430483 , Click to view
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Datasheet
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Shopping guide
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- Datasheet: Download PXB4010EV1.3G
- Chipdatas Part: CD93-PXB4010EV1.3G
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/13 19:01 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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