Description

Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages over legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges and throughout device service life for ease of design and highly uniform performance. All device versions have Schmitt trigger inputs for high noise immunity and only require VDD bypass capacitors.

Specifications and features

High-speed operation, DC to 150 Mbps. No start-up initialization required. Wide Operating Supply Voltage, 2.5–5.5 V. Up to 5000 VRMS isolation. 60-year life at rated working voltage. High electromagnetic immunity. Ultra low power (typical), 5 V Operation, 1.6 mA per channel at 1 Mbps, 5.5 mA per channel at 100 Mbps, 2.5 V Operation, 1.5 mA per channel at 1 Mbps, 3.5 mA per channel at 100 Mbps. Schmitt trigger inputs. Selectable fail-safe mode, Default high or low output (ordering option). Precise timing (typical), 10 ns propagation delay, 1.5 ns pulse width distortion, 0.5 ns channel-channel skew, 2 ns propagation delay skew, 5 ns minimum pulse width. Transient Immunity 50 kV/µs. AEC-Q100 qualification. Wide temperature range, -40 to 125 °C. RoHS-compliant packages, SOIC-16 wide body, SOIC-8 narrow body.

Application Scenarios

Industrial automation systems, Medical electronics, Hybrid electric vehicles, Isolated switch mode supplies, Isolated ADC, DAC, Motor control, Power inverters, Communications systems