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Description
The T91L30IQBF0724 is a fully integrated SONET/SDH transceiver designed for SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/STM-1 applications. It includes an on-chip Clock Multiplier Unit (CMU) and Clock and Data Recovery (CDR) function. The transceiver can be disabled and bypassed for external based received reference clock recovery.
Specifications and features
- Targeted for SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications
- Selectable full duplex operation between STS-12/STM-4 standard rate of 622.08 Mbps or STS-3/STM-1 155.52 Mbps
- Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serial-to-parallel converter, clock data recovery (CDR) functions, and a SONET/SDH frame and byte boundary detection circuit
- Ability to disable and bypass on-chip CDR for external-based received reference clock recovery through Differential LVPECL input pins XRXCLKIP/N
- 8-bit LVTTL parallel data bus paths running at 77.76 Mbps in STS-12/STM-4 or 19.44 Mbps in STS-3/STM-1 mode of operation
- Uses Differential LVPECL or Single-Ended LVTTL CMU reference clock frequencies of either 19.44 MHz or 77.76 MHz for both STS-12/STM-1 or STS-3/STM-1 operations
- Optional use of 77.76 MHz Single-Ended LVTTL input for independent CDR reference clock operation
- Able to detect and recover SONET/SDH frame boundary and byte align received data on the parallel bus
- Diagnostics features include LOS monitoring and automatic received data mute upon LOS
- Provides Local, Remote and Split Loop-Back modes as well as Loop Timing mode
- Optional flexibility to re-configure the transmit parallel bus clock output to a clock input and accept timing signal from the framer/mapper device to permit the framer/mapper device time domain to be synchronized with the transceiver transmit timing
- Meets Telcordia, ANSI, and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, Bellcore TR- NWT-000253 and GR-253-CORE, GR-253 ILR SONET Jitter specifications
- Complies with ANSI/TIA/EIA-644 and IEEE P1596.3 3.3V LVDS standard, 3.3V LVPECL, and JESD 8-B LVTTL and LVCMOS standard
- Operates at 3.3V Core with 3.3V I/O
- Less than 660mW in STS-3/STM-1 mode or 800mW in STS-12/STM-4 mode typical power dissipation
- Package: 10 x 10 x 2.0 mm 64-pin QFPApplication Scenarios
- SONET/SDH-based Transmission Systems
- Add/Drop Multiplexers
- Cross Connect Equipment
- ATM and Multi-Service Switches, Routers and Switch/Routers
- DSLAMS
- SONET/SDH Test Equipment
- DWDM Termination EquipmentComparison
Advantages- Fully integrated transceiver with on-chip Clock Multiplier Unit (CMU) and Clock and Data Recovery (CDR) function
- Ability to disable and bypass on-chip CDR for external-based received reference clock recovery
- Supports both STS-12/STM-4 and STS-3/STM-1 applications
- Wide range of operating frequencies and modes
- Reliable diagnostics features for LOS monitoring and automatic received data mute upon LOSDisadvantages- Power dissipation may be higher compared to other models
- Requires a specific package size (10 x 10 x 2.0 mm 64-pin QFP) -
Similar parts: 430483 , Click to view
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Datasheet
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Shopping guide
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- Datasheet: Download T91L30IQBF0724
- Chipdatas Part: CD93-T91L30IQBF0724
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/03 16:19 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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