Description

The RX8025TUB is an electronic component model belonging to the IC Chips product category. It provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus, and main memory. The RX8025TUB features a 60x processor interface with support for up to four 60x processors, various operating frequencies, and a 32-bit address bus and 64-bit data bus. It also supports full memory coherency and optional 60x local bus slave. The secondary (L2) cache control is configurable for write-through or write-back operation with cache sizes of 256 Kbytes, 512 Kbytes, and 1 Mbyte. The RX8025TUB has a memory interface with 1 Gbyte of RAM space, 16 Mbytes of ROM space, and supports fast page mode DRAMs, extended data out (EDO) DRAMs, and synchronous DRAMs (SDRAMs). The PCI interface is compliant with PCI Local Bus Specification, Revision 2.1 and supports PCI interlocked accesses to memory, big- or little-endian operation, and memory prefetching of PCI read accesses. Power management features include support for 60x nap, doze, and sleep power management modes and suspend mode. The RX8025TUB is packaged in a 304-pin ceramic ball grid array (CBGA) package.

Specifications and features

• 60x processor interface with support for up to four 60x processors
• Various operating frequencies and bus divider ratios
• 32-bit address bus, 64-bit data bus
• Supports full memory coherency
• Supports optional 60x local bus slave
• Decoupled address and data buses for pipelining of 60x accesses
• Store gathering on 60x-to-PCI writes
• Secondary (L2) cache control configurable for write-through or write-back operation
• Supports cache sizes of 256 Kbytes, 512 Kbytes, and 1 Mbyte
• Up to 4 Gbytes of cacheable space
• Direct-mapped cache
• Supports byte parity
• Supports partial update with external byte decode for write enables
• Programmable interface timing
• Supports pipelined burst, synchronous burst, or asynchronous SRAMs
• Alternately supports an external L2 cache controller or integrated L2 cache module
• Memory interface with 1 Gbyte of RAM space and 16 Mbytes of ROM space
• Supports parity or error checking and correction (ECC)
• High-bandwidth, 64-bit data bus (72 bits including parity or ECC)
• Supports fast page mode DRAMs, extended data out (EDO) DRAMs, and synchronous DRAMs (SDRAMs)
• Supports 1 to 8 banks of DRAM/EDO/SDRAM with sizes ranging from 2 Mbyte to 128 Mbytes per bank
• ROM space may be split between the PCI bus and the 60x/memory bus (8 Mbytes each)
• Supports 8-bit asynchronous ROM or 64-bit burst-mode ROM
• Supports writing to Flash ROM
• Configurable external buffer control logic
• Programmable interface timing
• PCI interface compliant with PCI Local Bus Specification, Revision 2.1
• Supports PCI interlocked accesses to memory using LOCK signal and protocol
• Supports accesses to all PCI address spaces
• Selectable big- or little-endian operation
• Store gathering on PCI writes to memory
• Only one external load presented by the RX8025TUB to the PCI bus
• Interface operates at 20–33 MHz
• Word parity supported
• 3.3 V/5.0 V-compatible
• Support for concurrent transactions on 60x and PCI buses
• Power management features
• Fully-static 3.3-V CMOS design
• Supports 60x nap, doze, and sleep power management modes and suspend mode
• IEEE 1149.1-compliant, JTAG boundary-scan interface
• 304-pin ceramic ball grid array (CBGA) package

Application Scenarios

The RX8025TUB can be used in various applications that require a high-bandwidth, high-performance interface between a 60x processor, secondary (L2) cache, PCI bus, and main memory. It is suitable for systems that require fast and efficient data processing, such as servers, workstations, and embedded systems.

Comparison

- Integrated high-bandwidth, high-performance interface
- Supports up to four 60x processors
- Supports full memory coherency
- Configurable secondary (L2) cache control
- Supports various cache sizes
- Supports parity or error checking and correction (ECC)
- High-bandwidth, 64-bit data bus
- Supports various types of DRAMs
- Compliant with PCI Local Bus Specification
- Power management features
- JTAG boundary-scan interface

- Limited cacheable space (up to 4 Gbytes)
- Limited ROM space (16 Mbytes)
- Supports only one external load presented to the PCI bus
- Interface operates at a limited frequency (20–33 MHz)