Description

The LCMXO640C-3MN0C is an electronic component model in the IC Chips category. It is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs. This model combines the best features of CPLD and FPGA devices on a single chip, making it suitable for glue logic, bus bridging, bus interfacing, power-up control, and control logic.

Specifications and features

- Non-volatile and infinitely reconfigurable
- Powers up in microseconds with instant-on feature
- No external configuration memory required
- Excellent design security with no interceptable bit stream
- Reconfigure SRAM based logic in milliseconds
- SRAM and non-volatile memory programmable through JTAG port
- Supports background programming of non-volatile memory
- Sleep Mode for up to 100x static current reduction
- TransFR™ Reconfiguration (TFR) allows in-field logic update while system operates
- High I/O to Logic Density with options ranging from 256 to 2280 LUT4s
- Extensive package options with 73 to 271 I/Os
- Density migration supported and lead-free/RoHS compliant packaging
- Embedded and Distributed Memory with up to 27.6 Kbits sysMEM™ Embedded Block RAM and up to 7.5 Kbits distributed RAM
- Dedicated FIFO control logic
- Flexible I/O Buffer with programmable sysIO™ buffer that supports a wide range of interfaces
- sysCLOCK™ PLLs with up to two analog PLLs per device for clock multiplication, division, and phase shifting
- System Level Support includes IEEE Standard 1149.1 Boundary Scan, onboard oscillator, and compatibility with 3.3V, 2.5V, 1.8V, or 1.2V power supply
- IEEE 1532 compliant in-system programming

Application Scenarios

The LCMXO640C-3MN0C is ideal for various application scenarios, including but not limited to:

• Glue logic implementation
• Bus bridging and interfacing
• Power-up control
• Control logic

Comparison

- Combines the best features of CPLD and FPGA devices

- Limited capacity compared to high-end FPGAs