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MC10E196FN - Brand New onsemi Delay Lines - Datasheet - Chipdatas
MC10E196FN
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MC10E196FN - Brand New onsemi Delay Lines

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Brand:onsemi
Category:Delay Lines
Chipdatas Part No.:CD87-MC10E196FN
Manufacturer Part No.:MC10E196FN
Datecode:09+
Package:28-LCC J-Lead
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  • Description

    The MC10E/100E196 is a programmable delay chip (PDC) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the logic symbol. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps. These two elements provide the E196 with a digitally-selectable resolution of approximately 20 ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on chip by a high signal on the latch enable (LEN) control. The FTUNE input takes an analog voltage and applies it to an internal linear ramp for reducing the 20 ps Least Significant Bit (LSB) minimum resolution still further. The FTUNE input is what differentiates the E196 from the E195. An eighth latched input, D7, is provided for cascading multiple PDC’s for increased programmable range. The cascade logic allows full control of multiple PDC’s, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 μF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation.

    Specifications and Features

    • 2.0 ns Worst Case Delay Range
    • ≈20 ps/Delay Step Resolution
    • Linear Input for Tighter Resolution
    • >1.0 GHz Bandwidth
    • On Chip Cascade Circuitry
    • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
    • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
    • Internal Input 50 kΩ Pulldown Resistors
    • ESD Protection:
    Human Body Model; > 1 kV,
    Machine Model; > 75 V
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
    For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL 94 V−0 @ 1.125 in, Oxygen Index: 28 to 34
    • Transistor Count = 425 devices
    • Pb−Free Packages are Available*

    Application Scenarios

    None

    Comparison

    None

    Advantages

    None

    Disadvantages

    None

  • Similar parts: 229 , Click to view
    Attributes Value
    Category Delay Lines
    Manufacturer onsemi
    Product Category Clock/Timing - Delay Lines
    Series 10E
    Packaging Tube
    Package-Case 28-LCC (J-Lead)
    Operating-Temperature 0°C ~ 85°C
    Mounting-Type Surface Mount
    Function Programmable
    Voltage-Supply 4.2 V ~ 5.7 V
    Supplier-Device-Package 28-PLCC (11.51x11.51)
    Number-of-Taps-Steps 128 Taps Steps
    Delay-to-1st-Tap 1.39ns
    Tap-Increment 20ps
    Available-Total-Delays 1.39ns ~ 3.63ns
    Number-of-Independent-Delays 1 Independent Delay
  • Datasheet
    Not found or temporary maintenance
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Additional Information
  • Datasheet: Download MC10E196FN
  • Chipdatas Part: CD87-MC10E196FN
  • Warehouse: China, Hong Kong
  • Dispatch: Within 24 hours
  • Free Shipping: Yes
  • Prority Shipping: Yes, 3-5 days
  • Last Updated: 2024/06/03 04:40 +0800
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