ISPPACCLK5610V-01T48I - Brand New LATTICE Clock Generators / Frequency Synthesizers / PLL
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Description
The ISPPACCLK5610V-01T48I is an electronic component model in the Clock Generators / Frequency Synthesizers / PLL product category. It is an in-system-programmable zero delay universal fan-out buffer designed for clock distribution applications. The first member of the ispClock5300S family, the ISPPACCLK5610V-01T48I provides up to 12 single-ended ultra low skew outputs. Each pair of outputs can be independently configured to support separate I/O standards and output frequencies. The configuration information is stored on-chip in non-volatile E2CMOS® memory.
Specifications and features
General Features:
- Four Operating Configurations: Zero delay buffer, Zero delay and non-zero delay buffer, Dual non-zero delay buffer, Non-zero delay buffer with output divider
- 8MHz to 267MHz Input/Output Operation
- Low Output to Output Skew (<100ps)
- Low Jitter Peak-to-Peak (< 70 ps)
Programmable Fan-out Buffers:
- Up to 20 programmable fan-out buffers with individual enable controls
- Programmable single-ended output standards (LVTTL, LVCMOS, HSTL, eHSTL, SSTL)
- Programmable output impedance (40 to 70Ω in 5Ω increments)
- Programmable slew rate
- Up to 10 banks with individual VCCO and GND (1.5V, 1.8V, 2.5V, 3.3V)
Integrated High-Performance PLL:
- Programmable lock detect
- Three "Power of 2" output dividers (5-bit)
- Programmable on-chip loop filter
- Compatible with spread spectrum clocks
- Internal/external feedback
Precision Programmable Phase Adjustment:
- 8 settings; minimum step size 156ps
- Locked to VCO frequency
- Up to +/- 5ns skew range
- Coarse and fine adjustment modes
Clock Frequency Domains:
- Up to three clock frequency domains
Clock Reference and External Feedback Inputs:
- Programmable single-ended or differential input reference standards
- Clock A/B selection multiplexer
- Programmable Feedback Standards
- Programmable termination
Other Features:
- All Inputs and Outputs are Hot Socket Compliant
- Full JTAG Boundary Scan Test In-System Programming Support
- Exceptional Power Supply Noise Immunity
- Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
- 48-pin and 64-pin TQFP Packages
Application Scenarios
The ISPPACCLK5610V-01T48I can be used in the following applications:
- Circuit board common clock distribution
- PLL-based frequency generation
- High fan-out clock buffer
- Zero-delay clock buffer
Comparison
Advantages:- Provides up to 12 single-ended ultra low skew outputs
- Independent configuration of output standards and frequencies
- On-chip storage of configuration information
- Programmable fan-out buffers with individual enable controls
- High-Performance PLL with various programmable features
- Precision programmable phase adjustment per output
- Hot Socket Compliant inputs and outputs
- Full JTAG Boundary Scan Test In-System Programming Support
- Exceptional Power Supply Noise Immunity
- Wide temperature range options (0 to 70°C and -40 to 85°C)
Disadvantages:- Limited to clock distribution applications
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Similar parts: 9857 , Click to view
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Datasheet
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Shopping guide
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Popular parts of the same kind
- Datasheet: Download ISPPACCLK5610V-01T48I
- Chipdatas Part: CD87-ISPPACCLK5610V-01T48I
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/26 09:09 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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