SI53304-B-GM - Brand New SILICON LABS Clock Buffers, Drivers
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Description
The SI53304-B-GM is an electronic component model that belongs to the clock buffers and drivers product category. It supports both single-ended or differential input clock signals and generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs. It provides signal level translation for differential to single-ended, single-ended to differential, differential to differential, and single-ended to single-ended signals. The model has a wide frequency range, achieving 5 to 710 MHz for LVPECL and LVDS, 5 to 250 MHz for HCSL, 5 to 350 MHz for SSTL and HSTL, and 5 to 200 MHz for CMOS. It also boasts an additive jitter of 150 fs RMS typ, output-output skew of 100 ps, and propagation delay of 2.5 ns typ. The core supply voltage is single, with excellent power supply rejection ratio (PSRR) of 1.8, 2.5, or 3.3 V. The output driver supply voltage is independent of core supply and can use 1.5, 1.8, 2.5, or 3.3 V. The model is designed with a loss of signal (LOS) indicator for system clock monitoring, and an output enable (OEB) pin for glitchless control of output clocks. It only consumes 10 mA typical core current, and has an industrial temperature range of –40 to +85 °C. The model is in a small size, measuring 24-lead, 4 x 4 mm QFN.
Specifications and features
• Supports single-ended or differential input clock signals.
• Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs.
• Provides signal level translation.
• Wide frequency range.
• Additive jitter: 150 fs RMS typ.
• Output-output skew: 100 ps.
• Propagation delay: 2.5 ns typ.
• Single core supply with excellent PSRR: 1.8, 2.5, or 3.3 V.
• Output driver supply voltage independent of core supply: 1.5, 1.8, 2.5, or 3.3 V.
• Loss of Signal (LOS) indicator allows system clock monitoring.
• Output Enable (OEB) pin allows glitchless control of output clocks.
• Low power: 10 mA typical core current.
• Industrial temperature range: –40 to +85 °C.
• Small size: 24-lead, 4 x 4 mm QFN.Application Scenarios
• High-Speed Clock Distribution.
• Ethernet Switch/Router.
• SONET / SDH.
• PCI Express 2.0/3.0.
• Fibre Channel.
• MSAN/DSLAM/PON.
• Telecom Line Cards.Comparison
Advantages- Supports both single-ended or differential input clock signals.
- Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs.
- Provides signal level translation for differential to single-ended, single-ended to differential, differential to differential, and single-ended to single-ended signals.
- Wide frequency range, achieving 5 to 710 MHz for LVPECL and LVDS, 5 to 250 MHz for HCSL, 5 to 350 MHz for SSTL and HSTL, and 5 to 200 MHz for CMOS.
- Additive jitter of 150 fs RMS typ.
- Output-output skew of 100 ps.
- Propagation delay of 2.5 ns typ.
- Single core supply with excellent power supply rejection ratio (PSRR) of 1.8, 2.5, or 3.3 V.
- Output driver supply voltage independent of core supply and can use 1.5, 1.8, 2.5, or 3.3 V.
- Has a loss of signal (LOS) indicator for system clock monitoring.
- Designed with an output enable (OEB) pin for glitchless control of output clocks.
- Low power consumption at 10 mA typical core current.
- Industrial temperature range of –40 to +85 °C.
- Small size, measuring 24-lead, 4 x 4 mm QFN.
DisadvantagesThere are no recorded disadvantages for the SI53304-B-GM electronic component model.
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Similar parts: 2580 , Click to view
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Datasheet
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Shopping guide
Delivery period:
- - Will ship out in 2-3 days
- - DHL Express: 3-7 business days
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Popular parts of the same kind
- Datasheet: Download SI53304-B-GM
- Chipdatas Part: CD82-SI53304-B-GM
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/12 19:33 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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The fee is charged according to the rule of PayPal.
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Western Union charge US$0.00 banking fee.
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