PI7C8148BNJ - Brand New Diodes Incorporated Interface - Specialized
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Description
Pericoms PI7C7100 is the first triple port PCI-to-PCI Bridge device designed to be fully compliant with the 32-Bit, 33 MHz implementation of the PCI Local Bus Specification, Revision 2.1. It supports synchronous bus transactions between devices on the primary bus and the secondary buses both operating at 33 MHz. The primary and the secondary buses can also operate in concurrent mode, resulting in additional increase in system performance.
Specifications and features
- All three ports compliant with the PCI Local Bus Specification, Revision 2.1
- Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.0
- 32-Bit Primary and two Secondary Ports
- Circular-Delta Bus Architecture
- Concurrent primary to secondary bus operation and independent intra-secondary port channel to reduce traffic on the primary port
- Provides arbitration for two sets of 8 secondary bus masters
- Support PCI transactions for: All I/O and memory commands, Type 1 to Type 0 configuration conversion (downstream only), Type 1 to Type 1 configuration forwarding, Type 1 to special cycle configuration conversion
- Supports posted memory write buffers in all directions
- Implements delayed transactions for all PCI configuration, I/O and memory read commands
- Supports positive medium decoding
- Enhanced address decoding: 32-Bit I/O address range, 32-Bit memory-mapped I/O address range, VGA addressing and VGA palette snooping, ISA-aware mode for legacy support in the first 64KB of I/O address range
- IEEE 1149.1 JTAG interface support
- Full scan support
- 3.3V core logic with 5V tolerant 3.3V PCI signaling interface
- 256-pin plastic PBGA package (NA256)
- Supports system transaction ordering rules
- Hot-Plug "Ready"
Application Scenarios
Triple port PCI-to-PCI Bridge increases the number of PCI slots that can be supported in a system. It provides one less device load on the primary bus and allows devices on secondary busses to independently communicate while the primary bus is busy. The integrated two-level programmable arbiter support for up to 8 devices on each secondary bus maximizes master device control. The synchronous clock operation on the primary and secondary busses enhances PCI bridge performance and efficiency through support for delayed transactions.
Comparison
Advantages- Increases the number of PCI slots that can be supported in a system
- Conserves board real estate and provides one less device load on the primary bus
- Increases overall system performance by reducing bus traffic on the primary bus
- Maximizes master device control with two-level programmable arbiter support for up to 8 devices on each secondary bus
- Enhances PCI bridge performance and efficiency through support for delayed transactions
DisadvantagesNo specific disadvantages have been mentioned for this product.
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Datasheet
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Shopping guide
Delivery period:
- - Will ship out in 2-3 days
- - DHL Express: 3-7 business days
- - DHL eCommerce: 12-22 business days
- - FedEx International Priority: 3-7 business days
- - EMS: 10-15 business days
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Shipping option:
DHL, FedEx, EMS, SF Express, and Registered Air MailShipping tracking:
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Popular parts of the same kind
- Datasheet: Download PI7C8148BNJ
- Chipdatas Part: CD93-PI7C8148BNJ
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/03 07:45 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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The fee is charged according to the rule of PayPal.
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Western Union charge US$0.00 banking fee.
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We recommend to use bank transfer for large orders to save on handling fees.
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