MPC184VFB - Brand New Freescale / NXP Specialized ICs
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1 Development History
The MPC180 is the first in the Smart Networks platform’s S1 family of security processors developed for the commercial networking market. It is derived from security technologies Motorola has developed over the past 30 years, primarily for government applications. The third-generation execution units (EUs) in the MPC180 have been previously used in products for wireless base stations and secure wire-line communication.
2 Typical Applications
The MPC180 is suited for applications such as the following:
• SOHO and low-end routers
• xDSL access equipment
• ISDN access equipment
• Wireless base stations
• Broadband access
• WAP gateways
• DSLAMS
• Customer premise equipment (CPE)3 Features
The MPC180 is a flexible and powerful addition to any networking system currently using Motorola’s MPC8xx or MPC826x family of PowerQUICC™ communication processors. The MPC180 is designed to off-load computationally intensive security functions such as key generation and exchange, authentication, and bulk data encryption. The MPC180 is optimized to process all of the algorithms associated with IPSec, IKE, WTLS/WAP and SSL/TLS. In addition, the MPC180 is the only security processor on the market capable of executing the elliptic curve cryptography that is especially important for secure wireless communications.
MPC180 features include the following:• Public key execution unit (PKEU), which supports the following:
— RSA and Diffie-Hellman
– Programmable field size 80- to 2048-bits
– 1024-bit signature time of 32ms
– 10 IKE handshakes/second
— Elliptic Curve operations in either F 2 m or F p
– Programmable field size from 55- to 511-bits
– 155-bit signature time of 11ms
– 30 IKE handshakes/second
• Data encryption standard execution units (DEUs)
— DES and 3DES algorithm acceleration
– Two key (K1, K2, K1) or Three key (K1, K2, K3)
— ECB and CBC modes for both DES and 3DES
— 15 Mbps 3DES-HMAC-SHA-1 (memory to memory)
• Message authentication unit (MAU)
— SHA-1 with 160-bit message digest
— MD5 with 128-bit message digest
— HMAC with either algorithm
• ARC four execution unit (AFEU)
— Implements a stream cipher compatible with the RC4 algorithm
— 40- to 128-bit programmable key
— 20 Mbps ARC Four performance (memory to memory)
• Random Number Generator (RNG)
— Supplies up to 160 bit strings at up to 5 Mbps data rate
• Input Buffer (4kbits)
• Output Buffer (4kbits)
• Glueless interface to MPC8xx system or MPC826x local bus (50MHz and 66MHz operation)
• DMA hardware handshaking signals for use with the MPC826x
• 1.8v Vdd, 3.3v I/O
• 100pin LQFP package
• HIP4 0.25mm process -
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Datasheet
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- Datasheet: Download MPC184VFB
- Chipdatas Part: CD86-MPC184VFB
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- Last Updated: 2024/06/24 21:25 +0800
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