Description

The LPC1759/58/56/54/52/51 are microcontrollers from NXP Semiconductors with an ARM Cortex-M3 processor. These microcontrollers are designed for embedded applications and feature low power consumption. The ARM Cortex-M3 processor provides system enhancements such as improved debugging features and a higher level of support block integration. The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz and the LPC1759 operates at CPU frequencies of up to 120 MHz. These microcontrollers have a built-in Memory Protection Unit (MPU) and Nested Vectored Interrupt Controller (NVIC) for better performance. The LPC1759/58/56/54/52/51 have a wide range of peripherals, including Ethernet MAC, USB Device/Host/OTG interface, General Purpose DMA controller, UARTs, CAN channels, SSP controllers, SPI interface, I2C-bus interfaces, I2S-bus interface, ADC, DAC, motor control PWM, Quadrature Encoder interface, general-purpose timers, general-purpose PWM, ultra-low power Real-Time Clock (RTC), and general-purpose I/O pins.

Specifications and features

• ARM Cortex-M3 processor, running at frequencies of up to 100 MHz (LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759).
• Memory Protection Unit (MPU) with eight regions.
• Built-in Nested Vectored Interrupt Controller (NVIC).
• Up to 512 kB on-chip flash programming memory.
• Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.
• In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
• 8-channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix.
• On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller.
• USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only.
• Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.
• CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.
• SPI controller with synchronous, serial, full duplex communication and programmable data length.
• Two SSP controllers with FIFO and multi-protocol capabilities.
• Two I2C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with multiple address recognition and monitor mode.
• On the LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control.
• 6 channel 12-bit ADC and 10-bit DAC.
• Motor control PWM and Quadrature Encoder interface.
• 4 general purpose timers, 6-output general purpose PWM.
• Ultra-low power Real-Time Clock (RTC) with separate battery supply.
• Up to 52 general purpose I/O pins.

Application Scenarios

The LPC1759/58/56/54/52/51 microcontrollers are suitable for a range of embedded applications such as eMetering, lighting, industrial networking, alarm systems, white goods, and motor control.

Comparison

• The ARM Cortex-M3 processor provides system enhancements such as improved debugging features and a higher level of support block integration.
• The built-in Memory Protection Unit (MPU) and Nested Vectored Interrupt Controller (NVIC) provide better performance.
• The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz and the LPC1759 operates at CPU frequencies of up to 120 MHz.
• The microcontrollers have a wide range of peripherals, including Ethernet MAC, USB Device/Host/OTG interface, General Purpose DMA controller, UARTs, CAN channels, SSP controllers, SPI interface, I2C-bus interfaces, I2S-bus interface, ADC, DAC, motor control PWM, Quadrature Encoder interface, general-purpose timers, general-purpose PWM, ultra-low power Real-Time Clock (RTC), and general-purpose I/O pins.

• Not suitable for high-performance applications that require a faster processor.
• Limited memory compared to some other microcontrollers on the market.
• It may not be the best fit for applications that require a lot of external interrupts.