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EP1S20F780C6N - Brand New Intel / Altera FPGAs (Field Programmable Gate Array) - Datasheet - Chipdatas
EP1S20F780C6N
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EP1S20F780C6N - Brand New Intel / Altera FPGAs (Field Programmable Gate Array)

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In Stock: 66, Ready for Immediate Shipping
Brand:Intel / Altera
Category:FPGAs (Field Programmable Gate Array)
Chipdatas Part No.:CD94-EP1S20F780C6N
Manufacturer Part No.:EP1S20F780C6N
Datecode:09+
Package:780-BBGA, FCBGA
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  • Description

    Electronic Component Model: EP1S20F780C6N. This datasheet describes configuration devices for SRAM-based look-up table (LUT) devices.

    Specifications and features

    Configuration devices for SRAM-based LUT devices offer the following features:

    • Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices
    • Easy-to-use four-pin interface
    • Low current during configuration and near-zero standby mode current
    • Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
    • Available in compact plastic packages
    • 8-pin plastic dual in-line (PDIP) package
    • 20-pin plastic J-lead chip carrier (PLCC) package
    • 32-pin plastic thin quad flat pack (TQFP) package
    • EPC2 device has reprogrammable flash configuration memory
    • 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface
    • Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
    • Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
    • Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
    • nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration

    Application Scenarios

    This electronic component model is commonly used in configuring Altera ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices.

    Comparison

    Advantages

    No current during configuration and near-zero standby mode current.

    Disadvantages

    This model requires programming support with the Altera Programming Unit.

  • Similar parts: 3140 , Click to view
    Attributes Value
    Category FPGAs (Field Programmable Gate Array)
    Manufacturer Intel / Altera
    Product Category FPGAs (Field Programmable Gate Array)
    Series Stratix®
    Product Stratix
    Packaging Tray
    Mounting-Style SMD/SMT
    Tradename Stratix
    Package-Case FBGA-780
    Operating-Temperature 0°C ~ 85°C (TJ)
    Mounting-Type Surface Mount
    Voltage-Supply 1.425 V ~ 1.575 V
    Supplier-Device-Package 780-FBGA (29x29)
    IC Number of Gates
    Number-of-I-O 586 I/O
    Number-of-LABs-CLBs 1846
    Number-of-Logic-Elements-Cells 18460
    Total-RAM-Bits 1669248 Bits
    Maximum Operating Temperature + 70 C
    Operating temperature range 0 C
    Operating-Supply-Voltage 1.5 V
    Operating-Supply-Current 65 mA
    Maximum-Operating-Frequency 100 MHz
    Input/output 586 I/O
    Number-of-Logic-Array-Blocks-LABs 1846
    Number-of-Logic-Elements 18460 Logic Elements
    Total-Memory 1669248 bit
  • Datasheet
    Not found or temporary maintenance
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Additional Information
  • Datasheet: Download EP1S20F780C6N
  • Chipdatas Part: CD94-EP1S20F780C6N
  • Warehouse: China, Hong Kong
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  • Last Updated: 2024/06/13 18:33 +0800
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