FW80321M600 - Brand New Intel Microprocessors
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Description
The Agere Systems Inc. FW801 device provides the analog physical layer functions needed to implement a one-port node in a cable-based IEEE 1394- 1995 and IEEE P1394a network.
Distinguishing Features
■ Compliant with IEEE P1394a Draft 2.0 Standard for a High Performance Serial Bus (Supplement)
■ Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders
■ While unpowered and connected to the bus, will not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port
■ Does not require external filter capacitors for PLL
■ Does not require a separate 5 V supply for 5 V link controller interoperability
■ Interoperable across 1394 cable with 1394 physical layers (PHY) using 5 V supplies
■ Interoperable with 1394 link-layer controllers using 5 V supplies
■ Device powerdown feature to conserve energy in battery-powered applications
■ Interface to link-layer controller supports Annex J electrical isolation as well as bus-keeper isolationFeatures
■ Provides one fully compliant cable port at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s
■ Fully supports Open HCI requirements
■ Supports arbitrated short bus reset to improve utilization of the bus
■ Supports ack-accelerated arbitration and fly-by concatenation
■ Supports connection debounce
■ Supports multispeed packet concatenation
■ Supports PHY pinging and remote PHY access packets
■ Fully supports suspend/resume
■ Supports PHY-link interface initialization and reset
■ Supports 1394a register set
■ Supports LPS/link-on as a part of PHY-link interface
■ Supports provisions of IEEE 1394-1995 Standard for a High Performance Serial Bus
■ Fully interoperable with FireWire† implementation of IEEE 1394-1995
■ Reports cable power fail interrupt when voltage at CPS pin falls below 7.5 V
■ Separate cable bias and driver termination voltage supply for portOther Features
■ 48-pin TQFP package
■ Single 3.3 V supply operation
■ Data interface to link-layer controller provided through 2/4/8 parallel lines at 50 Mbits/s
■ 25 MHz crystal oscillator and PLL provide transmit/receive data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s and link-layer controller clock at 50 MHz
■ Multiple separate package signals provided for analog and digital supplies and grounds -
Similar parts: 1471 , Click to view
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Datasheet
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Shopping guide
Delivery period:
- - Will ship out in 2-3 days
- - DHL Express: 3-7 business days
- - DHL eCommerce: 12-22 business days
- - FedEx International Priority: 3-7 business days
- - EMS: 10-15 business days
Shipping fee:
- - Automatic Email notification (above 5 times)
- - View in your order page
Shipping option:
DHL, FedEx, EMS, SF Express, and Registered Air MailShipping tracking:
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- - View in your order page
How to Buy:
- - In-stock, Add to cart > Check out > Submit order > Complete payment >Delivery.
- - Inquiry, Add to inquiry sheet/Submit bom/inquire file/Send email us > Quote > Place order > Complete payment >Delivery.
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Payment:
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- - Wire transfer, include Local bank transfer.
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Popular parts of the same kind
- Datasheet: Download FW80321M600
- Chipdatas Part: CD93-FW80321M600
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/07/01 05:20 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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The fee is charged according to the rule of PayPal.
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Western Union charge US$0.00 banking fee.
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We recommend to use bank transfer for large orders to save on handling fees.
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