PI7C9X20404GPBNBE - Brand New Diodes Incorporated Interface - Specialized
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Description
Electronic Component Model: PI7C9X20404GPBNBE is the first triple port PCI-to-PCI Bridge device designed to be fully compliant with the 32-Bit, 33 MHz implementation of the PCI Local Bus Specification, Revision 2.1. It supports synchronous bus transactions between devices on the primary bus and the secondary buses both operating at 33 MHz. The primary and the secondary buses can also operate in concurrent mode, resulting in additional increase in system performance. This device allows a master and a target device on the same secondary PCI bus to communicate even while the primary bus is busy.
Specifications and features
- All three ports compliant with the PCI Local Bus Specification, Revision 2.1
- Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.0
- 32-Bit Primary and two Secondary Ports
- Circular-Delta Bus Architecture
- Concurrent primary to secondary bus operation and independent intra-secondary port channel to reduce traffic on the primary port
- Provides arbitration for two sets of 8 secondary bus masters
- Supports various PCI transactions including I/O and memory commands, configuration conversion, special cycle configuration conversion, and more
- Supports posted memory write buffers in all directions
- Implements delayed transactions for all PCI configuration, I/O and memory read commands
- Supports positive medium decoding and enhanced address decoding
- Includes IEEE 1149.1 JTAG interface support and full scan support
- Features 3.3V core logic with 5V tolerant 3.3V PCI signaling interface
- Comes in a 256-pin plastic PBGA package (NA256)
- Supports system transaction ordering rules and is Hot-Plug "Ready"
Application Scenarios
PI7C9X20404GPBNBE is suitable for increasing the number of PCI slots that can be supported in a system. It can be used as a single device instead of two PCI-to-PCI Bridge devices, saving board real estate and reducing device load on the primary bus. The concurrent and intra-secondary bus communication allows devices on secondary busses to independently communicate while the primary bus is busy. It also provides integrated two-level programmable arbiter support for up to 8 devices on each secondary bus, maximizing master device control. The device operates synchronously on the primary and secondary busses and supports enhanced PCI bridge performance and efficiency through support for delayed transactions.
Comparison
Advantages- Increases the number of supported PCI slots
- Conserves board real estate
- Reduces device load on the primary bus
- Allows concurrent and independent communication on secondary busses
- Maximizes master device control with integrated arbiter support
- Supports delayed transactions for improved performance and efficiency
DisadvantagesThere are no specific disadvantages mentioned for this model.
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Similar parts: 4284 , Click to view
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Datasheet
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Shopping guide
Delivery period:
- - Will ship out in 2-3 days
- - DHL Express: 3-7 business days
- - DHL eCommerce: 12-22 business days
- - FedEx International Priority: 3-7 business days
- - EMS: 10-15 business days
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DHL, FedEx, EMS, SF Express, and Registered Air MailShipping tracking:
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- Datasheet: Download PI7C9X20404GPBNBE
- Chipdatas Part: CD93-PI7C9X20404GPBNBE
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/12 19:28 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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