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MC100EP40DTG - Brand New onsemi Clock Generators / Frequency Synthesizers / PLL - Datasheet - Chipdatas
MC100EP40DTG

MC100EP40DTG - Brand New onsemi Clock Generators / Frequency Synthesizers / PLL

In Stock:10 ,Ready for Immediate Shipping
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In Stock: 10, Ready for Immediate Shipping
Brand:onsemi
Category:Clock Generators / Frequency Synthesizers / PLL
Chipdatas Part No.:CD79-MC100EP40DTG
Manufacturer Part No.:MC100EP40DTG
Datecode:09+
Package:TSSOP-20
$22.76930 /pcs Each tube contains 75 pcs
≥1:
$22.76930
≥10:
$22.54160
≥50:
$22.31391
≥100:
$21.63083
Numbers (pcs) :
  • The MC100EP40 is a three-state phase-frequency detector for phase-locked loop applications that require a minimum phase and frequency difference during latching. The advanced design significantly reduces the deadband of the detector. For proper operation, the input edge rates of the R and V inputs should be less than 5 ns. The device is suitable for use with 3.3 V / 5 V supplies. When the frequency and/or phase of the reference (R) and feedback (FB) inputs are different, the differential UP (U) and DOWN (D) outputs will provide a pulse stream that, if subtracted and integrated, will provide the error voltage used to control the VCO. When the phase difference between the reference (R) and feedback (FB) inputs is equal to or less than 80 pS, the phase lock detection pin will indicate lock by a high state. As shown in Figure 2, the VTX (VTR, VTRbar, VTFB, and VTFBbar) pins provide an internal termination network for a 50-line impedance environment. the VTX pin requires an external draw current of VCC-2 V. If both differential VTR and VTR (or VTFB and VTFBbar) are shorted together, a 100-termination resistor compatible with LVDS signal receiver termination is provided. For more information on logic device termination, see AND8020. The VBB pin is available as an internally generated power supply for this device only. For single-ended input cases, connect an unused differential input to VBB as a switching reference voltage. vbb also re-biases the ac-coupled input. When in use, decouple VBB and VCC via a 0.01 F capacitor and limit the source or draw current to 0.5 mA. when not in use, VBB should be left open. For more information on phase-locked loop operation, see AND8040. special consideration should be given to differential inputs to prevent instability under no-signal conditions.
  • Similar parts: 9857 , Click to view
    Attributes Value
    Category Clock Generators / Frequency Synthesizers / PLL
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  • Datasheet: Download MC100EP40DTG
  • Chipdatas Part: CD79-MC100EP40DTG
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  • Last Updated: 2024/06/03 04:27 +0800
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