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SY10EL34LZC - Brand New Microchip Technology Clock Generators / Frequency Synthesizers / PLL - Datasheet - Chipdatas
SY10EL34LZC
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SY10EL34LZC - Brand New Microchip Technology Clock Generators / Frequency Synthesizers / PLL

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In Stock: 1087, Ready for Immediate Shipping
Brand:Microchip Technology
Category:Clock Generators / Frequency Synthesizers / PLL
Chipdatas Part No.:CD93-SY10EL34LZC
Manufacturer Part No.:SY10EL34LZC
Datecode:09+
Package:16-SOIC 0.154", 3.90mm Width
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  • DESCRIPTION

    The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL34/L under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current.
    The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.
    Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple EL34/Ls in a system.

    FEATURES

    ■ 3.3V and 5V power supply options
    ■ 50ps output-to-output skew
    ■ Synchronous enable/disable
    ■ Master Reset for synchronization
    ■ Internal 75KΩ input pull-down resistors
    ■ Available in 16-pin SOIC package

  • Similar parts: 9857 , Click to view
    Attributes Value
    Category Clock Generators / Frequency Synthesizers / PLL
    Manufacturer Microchip Technology
    Product Category Clock Generators and Frequency Synthesizers
    Series 10EL, Precision Edge®
    Type Clock Generator
    Packaging Tube
    Package-Case 16-SOIC (0.154", 3.90mm Width)
    Operating-Temperature 0°C ~ 85°C
    Mounting-Type Surface Mount
    Voltage-Supply 3 V ~ 3.8 V
    Supplier-Device-Package 16-SOIC
    PLL No
    Input ECL, PECL
    Output Clock
    Number-of-Circuits 1 Circuit
    Ratio of output to input 1899/12/30 1:03:00
    Differential-Input:Output Yes/Yes
    Frequency-Max -
    Divider-Multiplier Yes/No
  • Datasheet
    Not found or temporary maintenance
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Additional Information
  • Datasheet: Download SY10EL34LZC
  • Chipdatas Part: CD93-SY10EL34LZC
  • Warehouse: China, Hong Kong
  • Dispatch: Within 24 hours
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  • Last Updated: 2024/06/12 23:52 +0800
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