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Description
The W65C02S is a low power cost sensitive 8-bit microprocessor. It is a fully static core and the PHI2 clock can be stopped when it is in the high or low state. The variable length instruction set and manually optimized core size make it an excellent choice for low power System-on-Chip (SoC) designs.
WDC, a Fabless Semiconductor Company, provides packaged chips for evaluation or volume production. They also provide a Development System that includes a W65C02DB Developer Board, an In-Circuit Emulator (ICE) and the W65cSDS Software Development System.
Specifications and features
8-bit data bus
16-bit address bus provides access to 65,536 bytes of memory space
8-bit ALU, Accumulator, Stack Pointer, Index Registers, Processor Status Register
16-bit Program Counter
69 instructions
16 addressing modes
212 Operation Codes (OpCodes)
Vector Pull (VPB) output indicates when interrupt vectors are being addressed
WAit-for-Interrupt (WAI) and SToP (STP) instructions reduce power consumption, decrease interrupt latency, and provide synchronization with external events
Variable length instruction set provides for lower power and smaller code optimization over fixed length instruction set processors
Fully static circuitry
Wide operating voltage range, 1.8+/- 5%, 2.5+/- 5%, 3.0+/- 5%, 3.3+/ - 10%, 5.0+/- 5% specified
Low Power consumption, [email protected]
Application Scenarios
The W65C02S microprocessor is suitable for low power System-on-Chip (SoC) designs. It can be used in various electronic devices that require cost sensitivity and low power consumption.
Comparison
Advantages- Low power consumption
- Variable length instruction set for power optimization
- Wide operating voltage range
Disadvantages- None mentioned
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Datasheet
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