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Description
The JNIC-1560G is a programmable electrically erasable logic (PEEL™) array based on ICT's CMOS EEPROM technology. It provides architectural flexibility and speed for programmable logic designs, making it suitable for a wide variety of combinatorial, synchronous, and asynchronous logic applications. With 20 I/O pins, 2 input/global-clocks, and 40 registers/latches, the JNIC-1560G is the most powerful 24-pin PLD available today. It supports speeds as fast as 10ns/15ns and 71.4MHz.
Specifications and features
- CMOS Electrically Erasable Technology
- Reprogrammable in 24-pin DIP, SOIC, and 28-pin PLCC packages
- Optional JN package for 22V10 power/ground compatibility
- 20 I/Os, 2 inputs/clocks, 40 registers/latches
- 40 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
- Multiple output functions per cell
- D, T, and JK registers with special features
- Independent or global clocks, resets, presets, clock polarity, and output enables
- High-speed commercial and industrial versions
- Ideal for multiple PLDs, counters, complex state-machines, comparators, decoders, multiplexers, etc.
- Development and programming support available
Application Scenarios
- Programmable logic designs
- Combinatorial, synchronous, and asynchronous logic applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers, and other wide-gate functions
Comparison
Advantages- Architectural flexibility
- High-speed performance
- Wide variety of applications
- Development and programming support
Disadvantages- Limited pin compatibility
- Moderate power consumption
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Datasheet
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Shopping guide
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- Datasheet: Download JNIC-1560G
- Chipdatas Part: CD92-JNIC-1560G
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/14 02:31 +0800
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- Full or Partial Refund , If the item is not as described
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