GENERAL DESCRIPTION

The M2006-02 and -12 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation. They support both forward and inverse FEC (Forward Error Correction) clock multiplication ratios, which are pin-selected from pre- programming look-up tables.
The M2006-12 adds Hitless Switching and Phase Build-out to enable SONET (GR-253) / SDH (G.813) MTIE and TDEV compliance during reference clock reselection. Hitless Switching (HS) engages when a 4ns or greater clock phase change is detected.

FEATURES

• Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation, including:
• 255/238 (OTU1) Mapping and 238/255 De-mapping
• 255/237 (OTU2) Mapping and 237/255 De-mapping
• 255/236 (OTU3) Mapping and 236/255 De-mapping
• Supports input reference and VCSO frequencies up to 700MHz, supports loop timing modes
(Specify VCSO frequency at time of order)
• Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
• M2006-12 includes APC pin for Phase Build-out function (for absorption of the input phase change)
• Commercial and Industrial temperature grades
• Single 3.3V power supply
• Small 9 x 9 mm SMT (surface mount) package