V58C2256164SCI5 - Brand New PROMOS IC Chips
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Description
The V58C2256(804/404/164)S is a four bank DDR DRAM organized as 4 banks x 8Mbit x 8 (804), 4 banks x 4Mbit x 16 (164), or 4 banks x 16Mbit x 4 (404). It achieves high speed data transfer rates by prefetching multiple bits and synchronizing the output data to a system clock. All control and address circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions occur on both edges of DQS.
Specifications and features
High speed data transfer rates with system frequency up to 166 MHz. Data Mask for Write Control. Four Banks controlled by BA0 & BA1. Programmable CAS Latency: 2, 2.5. Programmable Wrap Sequence: Sequential or Interleave. Programmable Burst Length: 2, 4, 8 for Sequential Type, 2, 4, 8 for Interleave Type. Automatic and Controlled Precharge Command. Power Down Mode. Auto Refresh and Self Refresh. Refresh Interval: 8192 cycles/64 ms. Available in 66-pin 400 mil TSOP or 60 Ball SOC BGA. SSTL-2 Compatible I/Os. Double Data Rate (DDR). Bidirectional Data Strobe (DQS) for input and output data, active on both edges. On-Chip DLL aligns DQ and DQs transitions with CK transitions. Differential clock inputs CK and CK. Power Supply 2.5V ± 0.2V. QFC options for FET control. x4 parts.
Application Scenarios
Comparison
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Similar parts: 430483 , Click to view
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Datasheet
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Shopping guide
Delivery period:
- - Will ship out in 2-3 days
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Popular parts of the same kind
- Datasheet: Download V58C2256164SCI5
- Chipdatas Part: CD94-V58C2256164SCI5
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/05/21 05:08 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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The fee is charged according to the rule of PayPal.
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The fee is charged according to the rule of PayPal.
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Western Union charge US$0.00 banking fee.
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We recommend to use bank transfer for large orders to save on handling fees.
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