Description

The CY7C136-35JC is a high-speed CMOS 2K by 8 dual-port static RAM suitable for shared or buffered data applications, such as cache memory for DSP, bit-slice, or multiprocessor designs. It has true dual-ported memory cells that allow simultaneous reads of the same memory location, and two ports that enable independent access to any location in memory. The CY7C136-35JC can be used as a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in combination with the CY7C142/CY7C146 SLAVE dual-port device in systems requiring 16-bit or greater word widths. The device is fully asynchronous and has automatic power-down features, BUSY output flag, available in 48-pin DIP, 52-pin PLCC and 52-pin TQFP (CY7C136/146), and Pb-Free packages.

Specifications and features

• Product category: IC Chips
• Organization: 2K x 8
• Technology: CMOS
• Access time: 15 ns
• Operating power: max. 110 mA
• Features: dual-port, asynchronous operation, automatic power-down, BUSY output flag, INT flag (52-pin PLCC/PQFP versions)
• Package: 48-pin DIP (CY7C132/142), 52-pin PLCC and 52-pin TQFP (CY7C136/146)
• Pb-Free packages available

Application Scenarios

The CY7C136-35JC is suitable for use as a cache memory for DSP, bit-slice, or multiprocessor applications in systems requiring shared or buffered data. It can also be used as a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in combination with the CY7C142/CY7C146 SLAVE dual-port device in systems requiring 16-bit or greater word widths.

Comparison

• True dual-ported memory cells that allow simultaneous reads of the same memory location
• Two independent ports enabling independent access to any location in memory
• Fully asynchronous operation
• Automatic power-down features
• BUSY output flag indicating the status of the port and INT flag on 52-pin PLCC/PQFP versions

• Access time of 15 ns may not be fast enough for some high-speed applications