Description

The BU9543KV-E2 is a special purpose audio Integrated Circuit (IC) designed for digital signal processing. It is developed specifically for high-performance audio decoding applications such as Digital Versatile Disc (DVD), High-Definition Television (HDTV) and Advanced Set-top audio decoding. This IC is optimized with audio-specific peripherals and a customized memory configuration. It is programmable with Motorola’s certified software for Dolby AC-3 5.1 Channel Surround, Dolby Pro Logic, and MPEG1 Layer 2.

Specifications and features

The BU9543KV-E2 boasts the following features:

• Digital Signal Processing Core
• Efficient, object-code compatible, 24-bit DSP56000 family DSP engine
• Highly parallel instruction set with unique DSP addressing modes
• Two 56-bit accumulators including extension byte
• Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
• Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles
• 56-bit addition/subtraction in 1 instruction cycle
• Fractional and integer arithmetic with support for multi-precision arithmetic
• Hardware optimized for block-floating point Fast Fourier Transforms (FFT)
• Hardware nested DO loops
• Zero-overhead fast interrupts (2 instruction cycles)
• PLL-based clocking with a wide range of frequency multiplications (1 to 4096) and power-saving clock divider (2i : i = 0 to 15), which reduces clock noise
• Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories

Memory:

• Modified Harvard architecture allows simultaneous access to program and data memories
• 12800 × 24-bit on-chip Program ROM1
• 4096 × 24-bit on-chip X-data RAM and 3584 × 24-bit on-chip X-data ROM1
• 4352 × 24-bit on-chip Y-data RAM and 2048 × 24-bit on-chip Y-data ROM1
• 512 × 24-bit on-chip Program RAM and 64 × 24-bit bootstrap ROM
• As much as 2304 × 24 bits of X- and Y-data RAM can be switched to Program RAM, giving a total of 2816 × 24 bits of Program RAM

Peripheral and Support Circuits:

• SAI includes:
• Two receivers and three transmitters
• Master or slave capability
• I2S, Sony, and Matshushita audio protocol implementations
• Two sets of SAI interrupt vectors
• SHI features:
• Single master capability
• SPI and I2C protocols
• 10-word receive FIFO
• Support for 8-, 16- and 24-bit words
• Byte-wide Parallel Host Interface with DMA support capable of reconfiguration as fifteen General Purpose Input/Output (GPIO) lines
• DAX features one serial transmitter capable of supporting S/PDIF, IEC958, CP-340, and AES/EBU formats
• Eight dedicated, independent, programmable GPIO lines
• On-chip peripheral registers memory mapped in data memory space
• OnCE port for unobtrusive, processor speed-independent debugging
• Software programmable PLL-based frequency synthesizer for the core clock
• Power saving Wait and Stop modes
• Fully static, HCMOS design from specified operating frequency down to dc
• 100-pin plastic Thin Quad Flat Pack (TQFP) surface-mount package
• 5 V power supply

Application Scenarios

The BU9543KV-E2 is specifically designed for high-performance audio decoding applications such as Digital Versatile Disc (DVD), High-Definition Television (HDTV) and Advanced Set-top audio decoding.

Comparison

• Optimized for high-performance audio decoding applications, making it an ideal choice for Digital Versatile Disc (DVD), High-Definition Television (HDTV) and Advanced Set-top audio decoding applications.
• The modified Harvard architecture allows simultaneous access to program and data memories, resulting in faster processing times.

• It may not be suitable for applications outside of high-performance audio decoding.
• The 100-pin plastic Thin Quad Flat Pack (TQFP) surface-mount package may require additional space on a circuit board compared to other packages.