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Description
The QL201B0L is a 5,000 usable ASIC gate, 8,000 usable PLD gate member of the pASIC 2 family of FPGAs. This electronic component is designed to provide high speed, high usable density, low price, and flexibility in the same devices. With its flexibility and speed, the QL201B0L is an efficient and high-performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics.
Specifications and features
- Ultimate Verilog/VHDL Silicon Solution
- Abundant, high-speed interconnect eliminates manual routing
- Flexible logic cell provides high efficiency and performance
- Design tools produce fast, efficient Verilog/VHDL synthesis
- 16-bit counter speeds exceeding 200 MHz
- 5,000 usable gates, 8,000 usable PLD gates, 156 I/Os
- 3-layer metal ViaLink process for small die sizes
- 100% routable and pin-out maintainable
- Complex functions (up to 16 inputs) in a single logic cell
- High synthesis gate utilization from logic cell fragments
- Full IEEE Standard JTAG boundary scan capability
- Individually-controlled input/feedback registers and OEs on all I/O pins
Application Scenarios
- Electronic design using HDLs such as Verilog and VHDL
- Designs requiring high speed, high usable density, and flexibility
- Designs utilizing complex functions in a single logic cell
Comparison
Advantages- High usable density
- Low price
- Flexibility
- Efficient and high performance
- Fast and efficient Verilog/VHDL synthesis
Disadvantages- None mentioned
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Datasheet
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Shopping guide
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Additional Information
- Datasheet: Download QL201B0L
- Chipdatas Part: CD94-QL201B0L
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/13 16:38 +0800
Refund
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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