Description

This microcontroller is a 32-bit system-on-chip (SoC) device designed for mid-range engine control and automotive transmission control applications. It is compatible with devices in Freescale’s MPC5600 family and offers performance and capabilities beyond the MPC5632M devices. The microcontroller’s e200z4 host processor core is built on Power Architecture® technology, specifically designed for embedded applications. This core supports instructions for digital signal processing (DSP). The device features two levels of memory hierarchy, including 8 KB of instruction cache, backed by a 128 KB on-chip SRAM, and a 2 MB internal flash memory. It also includes a calibration bus for development, accessible only when using the Freescale VertiCal Calibration System.

Specifications and features

• 150 MHz e200z4 Power Architecture core
• Variable length instruction encoding (VLE)
• Superscalar architecture with 2 execution units
• Up to 2 integer or floating point instructions per cycle
• Up to 4 multiply and accumulate operations per cycle
• 2 MB on-chip flash memory with ECC and read-while-write (RWW)
• 128 KB on-chip SRAM with standby functionality (32 KB) and ECC
• 8 KB instruction cache (with line locking), configurable as 2- or 4-way
• 14 + 3 KB eTPU code and data RAM
• 4x4 crossbar switch (XBAR)
• 24-entry MMU
• 16-entry Memory Protection Unit (MPU)
• CRC unit with 3 submodules
• Junction temperature sensor
• Configurable interrupt controller (INTC) with non-maskable interrupt (NMI)
• 64-channel eDMA
• 3 eSCI modules
• 3 DSPI modules (2 of which support downstream Micro Second Channel [MSC])
• 3 FlexCAN modules with 64 message buffers each
• 1 FlexRay module (V2.1) up to 10 Mbit/s w/dual or single channel, 128 message objects, ECC
• 1 eMIOS with 24 unified channels
• 1 eTPU2 (second generation eTPU) with 32 standard channels and 1 reaction module (6 channels with 3 outputs per channel)
• 2 enhanced queued analog-to-digital converters (eQADCs) with forty 12-bit input channels (expandable to 56 channels), 6 command queues, trigger and DMA support, and 688 ns minimum conversion time
• On-chip CAN/SCI Bootstrap loader with Boot Assist Module (BAM)
• Nexus: Class 3+ for core; Class 1 for eTPU
• JTAG (5-pin)
• Development Trigger Semaphore (DTS) with EVTO pin for communication with external tool
• Clock generation with on-chip 4–40 MHz main oscillator and on-chip FMPLL (frequency-modulated phase-locked loop)
• Up to 112 general purpose I/O lines individually programmable as input, output, or special function with programmable threshold (hysteresis)
• Power reduction modes: slow, stop, and standby
• Flexible supply scheme with 5 V single supply (with external ballast) and multiple external supplies: 5 V, 3.3 V, and 1.2 V

Application Scenarios

This microcontroller is ideal for use in mid-range engine control and automotive transmission control applications. It offers enhanced performance and capabilities compared to previous models, making it suitable for a wide range of embedded applications in the automotive industry. The flexible supply scheme and power reduction modes also contribute to its suitability for various scenarios.

Comparison

• Compatible with devices in Freescale’s MPC5600 family
• Superior performance and capabilities compared to previous models
• 32-bit system-on-chip (SoC) device
• Supports Power Architecture® technology and instructions for digital signal processing (DSP)
• Two levels of memory hierarchy, including 8 KB instruction cache, 128 KB on-chip SRAM, and 2 MB internal flash memory
• Includes a calibration bus for development with the Freescale VertiCal Calibration System
• Wide range of on-chip modules and functions, including eSCI, DSPI, FlexCAN, FlexRay, eMIOS, and eQADC
• Flexible supply scheme with multiple external supply options
• Supports power reduction modes for energy efficiency

No specific disadvantages have been reported for this model at this time.