Description

The PCK2510S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PCK2510S operates at 3.3 V VCC and is input compatible with both 2.5 V and 3.3 V input voltage ranges. It also provides integrated series damping resistors that make it ideal for driving point-to-point loads.

Specifications and features

• Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications
• Spread Spectrum clock compatible
• Operating frequency 50 to 150 MHz
• (tphase error – jitter) at 100 to133 MHz = ±50 ps
• Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps
• Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
• Pin-to-pin skew < 200 ps
• Available in plastic 24-Pin TSSOP
• Distributes one clock input to one bank of ten outputs
• External Feedback (FBIN) terminal Is used to synchronize the outputs to the clock input
• On-Chip series damping resistors
• No external RC network required
• Operates at 3.3 V

Application Scenarios

The PCK2510S is specifically designed for use with synchronous DRAMs, making it ideal for applications requiring high-performance and low-jitter clock distribution. It is commonly used in PC100/PC133 SDRAM applications and is compatible with spread spectrum clocks. With its operating frequency of 50 to 150 MHz and various jitter specifications, it offers precise clock distribution in demanding scenarios.

Comparison

- High-performance clock distribution
- Low skew and low jitter
- Precise alignment of feedback output to clock input
- Input compatible with multiple voltage ranges
- Integrated series damping resistors for driving point-to-point loads

- Limited to use with synchronous DRAMs
- Only operates at 3.3 V