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Description
The GS8182D18BD-400I is a member of the SigmaRAM™ Family, a family of wide, very low voltage HSTL I/O SRAMs designed for high performance networking systems. It is a 18,874,368-bit (18Mb) SRAM that operates at the speeds needed to implement economical high performance networking systems. It is built in compliance with the SigmaQuad SRAM pinout standard for Separate I/O synchronous SRAMs.
Specifications and features
The GS8182D18BD-400I features a simultaneous Read and Write SigmaQuad™ Interface and a JEDEC-standard pinout and package. It has a dual Double Data Rate interface and byte Write controls that are sampled at data-in time. It supports a Burst of 2 Read and Write operation. The core power supply is 1.8 V +150/–100 mV. It has a 1.5 V or 1.8 V HSTL Interface and supports pipelined read operations. The GS8182D18BD-400I also has a ZQ mode pin for programmable output drive strength and is IEEE 1149.1 JTAG-compliant Boundary Scan. It is available in a 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package. Additionally, it is pin-compatible with future 36Mb, 72Mb, and 144Mb devices.
Application Scenarios
The GS8182D18BD-400I can be used in a variety of applications, including high performance networking systems that require low voltage and high speed SRAM.
Comparison
Advantages- Wide, low voltage HSTL I/O SRAM design - Simultaneous Read and Write SigmaQuad™ Interface - Dual Double Data Rate interface - Support for pipelined read operations - Programmable output drive strengthDisadvantages- Limited availability in terms of memory size (18Mb only) - Specific pinout and package -
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Datasheet
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- Datasheet: Download GS8182D18BD-400I
- Chipdatas Part: CD94-GS8182D18BD-400I
- Warehouse: China, Hong Kong
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- Last Updated: 2024/07/01 00:45 +0800
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