Description

The EPM3064ATC100-10N is a low-cost, high-performance electronic component. It is part of the MAX 3000A family of EEPROM-based programmable logic devices (PLDs) built on a MAX architecture developed by Altera. The MAX 3000A devices are fabricated with advanced CMOS technology and operate with a 3.3V supply voltage, providing up to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. This specific model is part of the -10 speed grade, which is compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.

Specifications and features

• High-performance, low-cost CMOS EEPROM-based PLDs built on a MAX architecture
• 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
• Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
• Enhanced ISP features, including an enhanced ISP algorithm for faster programming, an ISP_Done bit to ensure complete programming, and a pull-up resistor on I/O pins during in-system programming
• High-density PLDs ranging from 600 to 10,000 usable gates
• 4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz
• MultiVolt TM I/O interface enabling the device core to run at 3.3 V while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
• Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J-lead chip carrier (PLCC), and FineLine BGA TM packages
• Hot-socketing support
• Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
• Industrial temperature range
• PCI compatible
• Bus-friendly architecture including programmable slew-rate control and open-drain output option
• Programmable macrocell flip-flops with individual clear, preset, clock, and clock enable controls and programmable power-saving mode for a power reduction of over 50% in each macrocell
• Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
• Programmable security bit for protection of proprietary designs
• Enhanced architectural features, including 6 or 10 pin- or logic-driven output enable signals, two global clock signals with optional inversion, enhanced interconnect resources for improved routability, and programmable output slew-rate control
• Programming support with the Altera master programming unit (MPU), MasterBlaster TM communications cable, ByteBlasterMV TM parallel port download cable, BitBlaster TM serial download cable, and programming hardware from third-party manufacturers

Application Scenarios

The EPM3064ATC100-10N can be used in a variety of applications, including but not limited to:

• Consumer electronics
• Industrial automation
• Communications
• Automotive
• Medical devices

Comparison

• Low-cost
• High-performance
• 3.3-V in-system programmability (ISP)
• Built-in boundary-scan test (BST) circuitry
• Enhanced ISP features
• High-density
• Industrial temperature range
• PCI compatible
• Bus-friendly architecture
• Programmable macrocell flip-flops with individual controls
• Programmable power-saving mode
• Configurable expander product-term distribution
• Programmable security bit
• Enhanced architectural features

• None identified