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Description
The SSTV16857 is a 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC. The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. It is intended to be incorporated into standard DIMM designs defined by JEDEC, such as DDR SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTV16857 is intended to be used for SSTL_2 input and output signals. The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well.
Specifications and features
- Stub-series terminated logic for 2.5 V VDDQ (SSTL_2) - Optimized for DDR SDRAM applications - Inputs compatible with JESD8–9 SSTL_2 specifications - Flow-through architecture optimizes PCB layout - ESD classification testing exceeds 2000 V to HBM per method A114 - Latch-up testing exceeds 100 mA - Same form, fit, and function as SSTL16877 - Full DDR 200/266 solution @ 2.5 V when used with PCKV857 - Available in TSSOP-48, TVSOP-48, and 56 ball VFBGA packages
Application Scenarios
The SSTV16857 can be used in various applications including standard DIMM designs, DDR SDRAM, or SDRAM II Memory Modules. It is suitable for SSTL_2 input and output signals and is compatible with DRAM devices installed on the DIMM.
Comparison
Advantages- Supports class I for standard stub-series applications or capacitive loads - Operates between 2.3 V and 2.7 V - Master reset asynchronously resets all registers to zero - Fully differential clock for compatibility with DRAM devices - Supports asynchronous input pin for defined outputs even before stable clock supply
Disadvantages- Requires between 23 and 27 registered control and address lines for module incorporation - Two 14-bit wide devices needed for each module - Must change state on positive transition of CLK signal
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