Description

The ISPLSI2032VE-110LB49 is a high density programmable logic device that is compatible with both 3.3V and 5V systems. It features 32 registers, 32 universal I/O pins, two dedicated input pins, three dedicated clock input pins, one global OE input pin, and a global routing pool (GRP) that provides complete interconnectivity between these elements. The device offers in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. With non-volatile reprogrammability, the ISPLSI2032VE-110LB49 allows for truly reconfigurable systems.

Specifications and features

• SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC with 1000 PLD Gates
• 32 I/O Pins, Two Dedicated Inputs
• 32 Registers
• High Speed Global Interconnect
• Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
• Small Logic Block Size for Random Logic
• 100% Functional, JEDEC, and Pinout Compatible with ispLSI 2032V Devices
• 3.3V LOW VOLTAGE 2032 ARCHITECTURE that interfaces with standard 5V TTL devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY with a maximum operating frequency of 300 MHz and a propagation delay of 3.0 ns
• Electrically Erasable and Reprogrammable
• Non-Volatile and 100% Tested at Time of Manufacture
• In-System Programmable with 3.3V programmability using the TAP
• Open-Drain Output Option for Flexible Bus Interface Capability
• Increased Manufacturing Yields, Reduced Time-to-Market, and Improved Product Quality
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• Enhanced Pin Locking Capability
• Three Dedicated Clock Input Pins
• Synchronous and Asynchronous Clocks
• Programmable Output Slew Rate Control
• Flexible Pin Placement
• Optimized Global Routing Pool Provides Global Interconnectivity
• Lead-Free Package Options

Application Scenarios

Comparison