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INTRODUCTION
This datasheet comprises the specifications for the 28F002BC 2-Mbit flash memory. Section 1 provides an overview of the 2-Mbit flash memory, including applications, pinouts, and pin descriptions. Section 2 describes the memory organization in detail. Section 3 defines a description of the memory’s principles of operation. Finally, Section 4 details the memory’s operating specifications.
■ High Performance Read
- 80/120 ns Max Access Time 40 ns Max. Output Enable Time
■ Low Power Consumption
- 20 mA Typical Read Current
■ x8-Only Input/Output Architecture
- Space-Constrained 8-bit Applications
■ Optimized Array Blocking Architecture
- One 16-KB Protected Boot Block
- Two 8-KB Parameter Blocks
- One 96-KB Main Block
- One 128-KB Main Block
- Top Boot Location
■ Hardware Data Protection Feature
- Erase/Write Lockout during Power Transitions
- Absolute Hardware Protection for Boot Block
■ Software EEPROM Emulation with Parameter Blocks
■ Extended Cycling Capability
- 100,000 Block Erase Cycles
■ Automated Byte Write and Block Erase
■ Industry-Standard Command User Interface
- Status Registers
- Erase Suspend Capability
■ SRAM-Compatible Write Interface
■ Reset/Deep Power-Down Input
- 0.2 µA ICC Typical
- Provides Reset for Boot Operations
■ Industry-Standard Surface Mount Packaging
- 40-Lead TSOP
- 44-Lead PSOP
- 40-Lead PDIP
■ ETOX™ IV Flash Technology
- 5V Read
■ 12V Write and Block Erase
- VPP = 12V ±5% Standard
- VPP = 12V ±10% Option
■ Independent Software Vendor Support -
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