AD9516-3BCPZ

GENERAL DESCRIPTION

The AD9516-31 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on- chip VCO tunes from 1.75 GHz to 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz may be used.

FEATURES

Low phase noise, phase-locked loop
On-chip VCO tunes from 1.75 GHz to 2.25 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Auto and manual reference switchover/holdover modes
Autorecover from holdover
Accepts references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
3 pairs of 1.6 GHz LVPECL outputs
Each pair shares 1 to 32 dividers with coarse phase delay
Additive output jitter 225 fS rms
Channel-to-channel skew paired outputs <10 ps
2 pairs of 800 MHz LVDS clock outputs
Each pair shares two cascaded 1 to 32 dividers with coarse
phase delay
Additive output jitter 275 fS rms
Fine delay adjust (ΔT) on each LVDS output
Eight 250 MHz CMOS outputs (two per LVDS output)
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs as needed
Serial control port
64-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
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