GL850GC

CHAPTER 1 GENERAL DESCRIPTION

GL850G is Genesys Logic’s advanced version Hub solutions which fully comply with Universal Serial Bus Specification Revision 2.0. GL850G embeds an 8-bit RISC processor to manipulatethe control/status registers and respond to the requests from USB host. Firmware of GL850G will control its general purpose I/O (GPIO) to access the external EEPROM and then respond to the host the customized PID and VID configured in the external EEPROM. Default settings in the internal mask ROM is responded to the host without having external EEROM. GL850G
is designed for customers with much flexibility. The more complicated settings such as PID, VID, and number of downstream ports settings are easily achieved byprogramming the external EEPROM (Ref. to Chapter 5).

• Compliant to USB specification Revision 2.0

− Support 4/3/2 downstream ports by I/O pin configuration
− Upstream port supports both high-speed (HS) and full-speed (FS) traffic
− Downstream ports support HS, FS, and low-speed (LS)traffic
− 1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload)
− Backward compatible to USB specification Revision 1.1
• On-chip 8-bit micro-processor
− RISC-like architecture
− USB optimized instruction set
− Performance: 6 MIPS @ 12MHz
− With 64-byte RAM and 2K mask ROM
− Support customized PID, VID by reading external EEPROM
− Support downstream port configuration by reading external EEPROM
• Single Transaction Translator (STT)
− Single TT shares the same TT control logics for alldownstream port devices. This is the most costeffective solution for TT. Multiple TT provides individual TT control logics for each downstream port.This is a performance better choice for USB 2.0 hub. Please refer to GL852 datasheet for more
detailed information.
• Integrate USB 2.0 transceiver