D003

General Description

The VSB Receiver(GDC21D003) is an ATSC compliant single chip communications device that synchronizes, equalizes, and corrects errors of ATSC 8/16 VSB and MMDS (Multichannel Multipoint Distribution System) 2/4/8/16 VSB modulated signal.

Features

General features
• ATSC compliant 8/16 VSB receiver
• MMDS 2/4/8/16 VSB receiver
• SNR threshold 14.9 dB on AWGN channel
• Tri-state parallel/serial MPEG-2 transport interface
• Supports I2C bus interface
• Boundary Scan Test circuit complies with IEEE Std. 1149.1 ID-Code = 0D0031C1
• Operating voltage : 3.3V
• 0.35µm CMOS technology
• 128 pin HQFP package

ADC

• Resolution : 10bits (£ ±1¤2 LSB DNL error)
• Sampling rate : 10.76 Msps
• Differential input range : 2Vpp(1.7 ± 0.5V differential)

Clock Divider

• Generates symbol clock(10.76MHz)
• Uses one of two VCXOs, fs(10.76MHz) and 2fs(21.52MHz) as input

Synchronizer

• Input control
• DC reduction and polarity correction
- Correction of polarity ambiguity caused by FPLL
• Non-coherent and coherent automatic gain control (AGC)
• Data Segment Sync and Field Sync recovery
• Timing recovery
• Polarity decision
- Polarity decision after Data Segment Sync is locked
• VSB mode detection
• Comb control
- Comb filter for the rejection of NTSC co-channel interface

Equalizer

• Decision feedback equalizer
• Supports training sequence and blind equalization
• Concurrent coefficients update in symbol time
• Available 3 different step-size
• Capability of reading equalizer coefficients
• Ghost cancellation in the range from -2.86ms to 20.76ms

Phase Tracker

• Intelligent loop control according to noise environment
• Phase tracking from -60° to 60° with resolution of 0.004 degree
• Phase, offset, and gain correction at a time

Channel Decoder

• Concatenated Viterbi/Reed-Solomon Decoder with Deinterleaver and Derandomizer
• Internal segment error counter
• Tri-state parallel/serial MPEG-2 Transport Demultiplexer interface