Description

The LCMXO1200C-4FTN256C-3I is an electronic component model categorized under IC Chips. It is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs. It is designed for glue logic, bus bridging, bus interfacing, power-up control, and control logic. This device combines the best features of CPLD and FPGA devices in a single chip.

Specifications and features

• Non-volatile, Infinitely Reconfigurable

• Instant-on – powers up in microseconds

• Single chip, no external configuration memory required

• Excellent design security, no bit stream to intercept

• Reconfigure SRAM based logic in milliseconds

• SRAM and non-volatile memory programmable through JTAG port

• Supports background programming of non-volatile memory

• Sleep Mode - Allows up to 100x static current reduction

• TransFR™ Reconfiguration (TFR) - In-field logic update while system operates

• High I/O to Logic Density: - 256 to 2280 LUT4s - 73 to 271 I/Os with extensive package options - Density migration supported - Lead free/RoHS compliant packaging

• Embedded and Distributed Memory: - Up to 27.6 Kbits sysMEM™ Embedded Block RAM - Up to 7.5 Kbits distributed RAM - Dedicated FIFO control logic

• Flexible I/O Buffer - Programmable sysIO™ buffer supports wide range of interfaces: - LVCMOS 3.3/2.5/1.8/1.5/1.2 - LVTTL - PCI - LVDS, Bus-LVDS, LVPECL, RSDS

• sysCLOCK™ PLLs: - Up to two analog PLLs per device - Clock multiply, divide, and phase shifting

• System Level Support: - IEEE Standard 1149.1 Boundary Scan - Onboard oscillator - Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply - IEEE 1532 compliant in-system programming

Application Scenarios

The LCMXO1200C-4FTN256C-3I can be used in various scenarios including glue logic, bus bridging, bus interfacing, power-up control, and control logic applications.

Comparison

The LCMXO1200C-4FTN256C-3I offers the following advantages:

• Non-volatile and infinitely reconfigurable

• Instant-on power-up in microseconds

• No external configuration memory required

• Excellent design security

• Supports background programming of non-volatile memory

• Sleep mode for static current reduction

• In-field logic update while system operates

• High I/O to Logic Density

• Embedded and distributed memory

• Flexible I/O buffer with support for various interfaces

• sysCLOCK PLLs for clock multiply, divide, and phase shifting

• System level support including boundary scan and in-system programming

There are no specific disadvantages mentioned for the LCMXO1200C-4FTN256C-3I model.