Description

The MPC860ENZQ66D4 is a PowerQUICC™ Quad Integrated Communications Controller that combines a microprocessor and peripheral functions, which is designed for various controller applications, especially in the fields of networking and communication systems.

Specifications and features

• 32-bit, single-issue, 32-bit general-purpose registers (GPRs) embedded MPC8xx core (PowerPC architecture) with branch prediction, conditional prefetch, and without conditional execution
• Support for 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)
• 16-Kbyte instruction caches are four-way, set-associative, with 256 sets
• 4-Kbyte instruction caches are two-way, set-associative, with 128 sets
• 8-Kbyte data caches are two-way, set-associative, with 256 sets
• 4-Kbyte data caches are two-way, set-associative, with 128 sets
• Cache coherency for instruction and data caches is maintained on 128-bit (four-word) cache blocks
• MMUs with 32-entry TLB, fully associative instruction, and data TLBs. Supports multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes, 16 virtual address spaces, and 16 protection groups
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) and 32 address lines
• Memory controller (eight banks), containing a complete dynamic RAM controller
• Four baud-rate generators (BRGs), four serial communications controllers (SCCs), and two SMCs (serial management channels)
• PCMCIA interface that supports two independent PCMCIA sockets and eight memory or I/O windows supported
• 357-pin ball grid array (BGA) package

Application Scenarios

The MPC860ENZQ66D4 microprocessor is a versatile one-chip integrated solution that excels in both communications and networking systems and can be particularly useful in various controller applications.

Comparison

• Dynamically-sized data bus for 8, 16, or 32 bits
• Support for multiple page sizes, virtual addresses, and protection groups
• Four SCCs, two SMCs, and 32-entry TLB
• Memory controller with eight banks, including a complete dynamic RAM controller

• Low clock speed for PowerPC architecture: only up to 80 MHz
• Not suited for applications with larger computing needs due to a single-issue core
• Relatively inconvenient packaging with a 357-pin ball grid array (BGA)