Description

The LFXP2-17E-5FN484C is an Electronic Component Model in the category of FPGAs (Field Programmable Gate Array).

Specifications and features

The EP300 PowerPC bus arbiter provides all the necessary functions to arbitrate multiple bus masters directly connected to the PowerPC host bus. The arbiter supports separate address and data bus tenure to realize the high performance allowed by the PowerPC bus architecture. At any given cycle, up to two simultaneous bus accesses are allowed.

The features of LFXP2-17E-5FN484C include:

• Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
• Supports up to eight PowerPC bus masters with unlimited slave device support.
• Supports two outstanding bus accesses.
• Supports address only transfer and address bus retry.
• Independent address bus and data bus tenure with separate bus grant and data bus grant.
• Option for fixed priority assignment or rotating priority scheme.
• Designed for ASIC or programmable logic device implementations in various system environments.
• Fully static design with edge triggered flip-flops.
• Optimized for ispXPGA product family.

Application Scenarios

The LFXP2-17E-5FN484C can be used in various applications that require the arbitration of multiple bus masters connected to the PowerPC host bus. It is suitable for ASIC or programmable logic device implementations in different system environments.

Comparison

- Provides all the necessary functions to arbitrate multiple bus masters directly connected to the PowerPC host bus.

- Supports up to eight PowerPC bus masters with unlimited slave device support.

- Supports two outstanding bus accesses.

- Supports address only transfer and address bus retry.

- Independent address bus and data bus tenure with separate bus grant and data bus grant.

- Option for fixed priority assignment or rotating priority scheme.

- Designed for ASIC or programmable logic device implementations in various system environments.

- Fully static design with edge triggered flip-flops.

- Optimized for ispXPGA product family.

- Not suitable for applications that do not require bus arbitration.