PM6352A-FGI

DESCRIPTION

The PM6341 E1 Framer/Transceiver (E1XC) is a feature-rich device suitable for use in many E1 systems (such as CSU, DSU, CH BANK, MUX, DPBX, DACS, and ESDX) with a minimum of external circuitry. The E1XC is software configurable, allowing feature selection without changes to external wiring.
On the receive side, the E1XC recovers clock and data and can be configured to frame to a basic G.704 2048 kbit/s signal or also frame to the signalling multiframe alignment signal and the CRC multiframe alignment signal.

FEATURES

• Integrates a full-featured E1 transceiver in a single device with analog circuitry for receiving and transmitting G.703 2048 kbit/s compatible signals and digital circuitry for terminating the duplex digital signal.
• Pin compatible with the PMC PM4341A T1 Framer/Transceiver device.
• Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring.
• Low power CMOS technology.
• Available in either a 68 pin PLCC or an 80 pin PQFP package.

The receiver section:

• Provides analog circuitry for receiving a G.703 2048 kbit/s signal with up to 6 dB of cable attenuation. Direct digital inputs are also provided to allow for bypassing the analog front-end.
• Recovers clock and data using a digital phase locked loop for high jitter tolerance. A direct clock input is provided to allow clock recovery to be bypassed.
• Accepts dual rail or single rail digital PCM inputs.
• Supports HDB3 or AMI line code.
• Accepts gapped data streams to support higher rate demultiplexing.
• Frames to a G.704 2048 kbit/s signal within 1 ms.
• Frames to the signalling multiframe alignment when enabled.
• Frames to the CRC multiframe alignment when enabled.
• Provides loss of signal detection, and indicates loss of frame alignment (OOF), loss of signalling multiframe alignment and loss of CRC multiframe alignment.
• Supports line and path performance monitoring according to ITU-T recommendations. Accumulators are provided for counting:
• CRC-4 errors to 1000 per second;
• Far end block errors to 1000 per second;
• Frame sync errors to 127 per second; and
• Line code violations to 8191 per second.
• Indicates the reception of remote alarm and remote multiframe alarm.
• Indicates the reception of alarm indication signal (AIS) and time slot 16 AIS.
• Declares RED and AIS alarms using Q.516 recommended integration periods.
• Provides an HDLC/LAPD interface for terminating a data link. Supports polled, interrupt-driven, or DMA servicing of the HDLC interface.
• Optionally extracts the data link from timeslot 16 (64 kbit/s), which may be used to receive common channel signalling, or from any combination of the national bits in timeslot 0 of non-frame alignment signal frames (4 kbit/s - 20 kbit/s).
• Provides a two-frame elastic store buffer for jitter and wander attenuation that performs controlled slips and indicates slip occurrence and direction.
• Provides channel associated signalling extraction, with optional data inversion, programmable idle code substitution, and up to 3 multiframes of signalling debounce on a per-timeslot basis.
• Provides trunk conditioning which forces programmable trouble code substitution and signalling conditioning on all timeslots or on selected timeslots.
• Optionally provides dual rail digital PCM output signals to allow BPV transparency. Also supports unframed mode.
• Supports transfer of received PCM and signalling data to 2048 kbit/s backplane buses.

APPLICATIONS

• E1 ATM Interfaces
• E1 Frame Relay Interfaces
• E1 & E3 Multiplexers (MUX)
• Digital Private Branch Exchanges (DPBX)
• Digital Access and Cross-Connect Systems (DACS)
• Electronic Cross-Connect Systems (EDSX)
• E1 & E3 Test Equipment (TEST)
• ISDN Primary Rate Interfaces (PRI)
• E1 Channel Service Units (CSU) and Data Service Units (DSU)
• SONET/SDH Add/Drop Multiplexers (ADM)