EP7212-CV-D

OVERVIEW

The EP7212 is designed for ultra-low-power applications such as organizers / PDAs, two-way pagers, smart cellular phones or any vertical PDA device that features the added capability of digital audio decom pression. The core-logic functionality of the device is built around an ARM720T processor with 8 K-bytes of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU) which allows for support of sophisticated operating systems like Microsoft Windows CE.

FEATURES

■ ARM720T processor
— ARM7TDMI CPU
— 8 K-bytes of four-way set-associative cache
— MMU with 64-entry TLB (transition look-aside buffer)
— Write Buffer
— Windows CE enabled
— Thumb code support enabled
■ Dynamically programmable clock speeds of 18, 36, 49, and 74 MHz at 2.5 V
■ Performance matching 100-MHz Intel Pentium-based PC
■ Ultra low power
— Designed for applications that require long battery life while using standard AA/AAA batteries or rechargeable cells
— Typical Power Numbers
● 90 mW at 74 MHz in the Operating State
● 30 mW at 18 MHz in the Operating State
● 10 mW in the Idle State (clock to the CPU stopped, everything else running)
● <1 mW in the Standby State (realtime clock ‘on’, everything else stopped)
■ Advanced audio decoder / decompression capability
— Allows for support of multiple audio decompression algorithms
— Supports MPEG 1, 2, & 2.5 layer 3 audio decoding, including ISO compliant MPEG 1 & 2 layer 3 support for all standard sample rates and bit rates
— Supports bit streams with adaptive bit rates
— DAI (Digital Audio Interface) providing glueless interface to low-power DACs, ADCs, and Codecs
■ LCD controller
— Interfaces directly to a single-scan panel monochrome LCD
— Panel width size is programmable from 32 to 1024 pixels in 16-pixel increments
— Video frame buffer size programmable up to 128 kbytes
— Bits per pixel of 1, 2, or 4 bits
■ DRAM controller
— Supports both 16- and 32-bit-wide DRAMs
— EDO support (Fast Page Mode support for 13 MHz and 18 MHz operation only)
■ Memory controller
— Decodes up to 6 separate memory segments of up to 256 Mbytes each
— Each segment can be configured as 8, 16, or 32 bits wide and supports page- mode access
— Programmable access time for conventional ROM / SRAM / FLASH memory
— Supports Removable FLASH card interface
— Enables connection to removable FLASH card for addition of expansion FLASH memory modules
■ 38,400 bytes (0x9600) of on-chip SRAM for fast program execution and / or as a frame buffer
■ Synchronous serial interface
— ADC (SSI) Interface: Master mode only; SPI and Microwire1-compatible (128 kbps operation)
■ On-chip ROM; for manufacturing support
■ 27-bits of general-purpose I/O
— Three 8-bit and one 3-bit GPIO port
— Supports scanning keyboard matrix
■ Two UARTs (16550 type)
— Supports bit rates up to 115.2 kbps
— Contains two 16-byte FIFOs for TX and RX
— UART1 supports modem control signals
■ SIR (up to 115.2 kbps) infrared encoder / decoder
— IrDA (Infrared Data Association) SIR protocol encoder / decoder
■ DC-to-DC converter interface (PWM)
— Provides two 96-kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a DC to DC converter
■ Two timer counters
■ 208-pin LQFP or new 256-ball PBGA packages
■ Evaluation kit available with BOM, schematics, sample code, and design database
■ Support for up to two ultra-low-power CL-PS6700 PC Card controllers
■ Dedicated LED flasher pin from RTC
■ Full JTAG boundary scan and Embedded ICE support
■ Commercial operating temperature range