NB100LVEP222MNG

The NB100LVEP222 is a low skew 2:1:15 differential 1-drop/2-drop ECL fan-out buffer for clock distribution. LVECL/LVPECL input signal pairs are available in differential configuration or single-ended (VBB output reference bypassed and connected to a pair of unused inputs). One of two fully differential clock inputs can be selected. Each of the four output groups consisting of 2, 3, 4, and 6 differential pairs can be independently configured to fan-out 1X or 1/2X of the input frequency. data can also be distributed when the output group is configured in 1-division mode. the LVEP222 specifically guarantees low output-output skew. Optimized design, layout, and processing minimize intra-device and batch-to-batch skew. This device is an improved version of the MC100LVE222 with higher speed capability and reduced skew. fsel pin and CLK_Sel pin are asynchronous control inputs. Any change may result in an uncertain output state, requiring an MR pulse to resynchronize any 1/2X output (see Figure 4). Unused outputs correspond to remaining unterminated (open) to reduce power consumption and switching noise. nb100lvep222, like most ECL devices, can be operated in LVPECL mode, based on a positive VCC/VCC0 supply. Therefore, the LVEP222 can be used in 2.5/3.3 V systems for high performance clock distribution. In PECL environments series or Davinan lines are typically used terminated because they require no additional power supply. For more information on using PECL, designers should refer to application note AN1406/D. For SPICE signals, refer to application note AN1560/D. Only the VBB pin, the internally generated supply voltage, is provided for this device. For single-ended LVPECL inputs, an unused differential input is coupled to VBB as the switching reference voltage. vbb also re-biases the AC coupled input. When used, VBB is decoupled from VCC/VCC0 by a 0.01 uF capacitor and limits the current source or receives 0.5 mA of current. When not in use, VBB should be left open.