MC100EP196BMNG

The MC100EP196B is a programmable delay chip (PDC) mainly used for clock de-skewing and timing adjustment. It provides variable delays for differential NECL/PECL input conversion. It is similar in structure to the EP195, but adds further trimming in the delay using the FTUNE pin. the FTUNE input uses an analog voltage from VCC to VEE to trim the output delay from 0 to 60 ps. the delay section consists of a programmable gate and multiplexer matrix, as shown in the logic diagram in Figure 2. The EP196B delay increments have a digitally selectable resolution of approximately 10 ps, with a net range of up to 10.4 ns. The desired delay is selected by the 10 data selection inputs D(9:0) values, controlled by LEN (pin 10). a low level on LEN enables a transparent loading mode for the real-time delay values determined by D(9:0). a low-to-high transition on LEN will latch against any subsequent change in D(10.0). 0) for any subsequent changes in D(10: 0) and maintains the existing current value. Table 6 and Figure 3 show the proper delay values for the various tap counts associated with D0 (LSB) through D9 (MSB).