EP3SE110F780C4N

EP3SE110F780C4N Description

Based on a full-layer copper SRAM process, the Stratix® III family offers one of the industry's most advanced high-performance, low-power FPGAs. The Altera EP3SE110F780C4N is part of the Stratix® III family, designed for fast system integration and capable of delivering best-in-class signal integrity.The Altera EP3SE110F780C4N has a total memory of up to 8727 kbit.

EP3SE110F780C4N Features

■ Selectable Core Voltage, available in low-voltage devices (L ordering code suffix), enables selection of lowest power or highest performance operation
■ Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per device
■ Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration, clock switchover, programmable bandwidth, clock synthesis, and dynamic phase shifting
■ Memory interface support with dedicated DQS logic on all I/O banks
■ Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks
■ Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide range of industry I/O standards
■ Dynamic On-Chip Termination (OCT) with auto calibration support on all I/O banks
■ High-speed differential I/O support with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry for 1.6 Gbps performance
■ Support for high-speed networking and communications bus standards including SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI
■ The only high-density, high-performance FPGA with support for 256-bit AES volatile and non-volatile security key to protect designs
■ Robust on-chip hot socketing and power sequencing support
■ Integrated cyclical redundancy check (CRC) for configuration memory error detection with critical error determination for high availability systems support
■ Built-in error correction coding (ECC) circuitry to detect and correct data errors in M144K TriMatrix memory blocks
■ Nios® II embedded processor support
■ Support for multiple intellectual property megafunctions from Altera® MegaCore® functions and Altera Megafunction Partners Program (AMPPSM)

■ 48,000 to 338,000 equivalent logic elements (LEs) ( refer to Table 1–1)
■ 2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers
■ High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18, and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
■ I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for robust signal integrity
■ Programmable Power Technology, which minimizes power while maximizing device performance

EP3SE110F780C4N Applications

■ High-performance logic
■ Digital signal processing (DSP)
■ Embedded designs