HD6433040SA00F

Overview

The H8/3048 Group is a series of microcontrollers (MCUs) that integrate system supporting
functions together with an H8/300H CPU core having an original Renesas Technology architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory
access controller (DMAC), a refresh controller, and other facilities.
The four members of the H8/3048 Group are the H8/3048, the H8/3047, H8/3045, and the
H8/3044. The H8/3048 has 128 kbytes of ROM and 4 kbytes of RAM. The H8/3047 has 96 kbytes
of ROM and 4 kbytes of RAM. The H8/3045 has 64 kbytes of ROM and 2 kbytes of RAM. The
H8/3044 has 32 kbytes of ROM and 2 kbytes of RAM.
Seven MCU operating modes offer a choice of data bus width and address space size. The modes
(modes 1 to 7) include one single-chip mode and six expanded modes. In addition to the mask ROM versions of the H8/3048 Group, the H8/3048 has a ZTATô1 version with user-programmable on-chip PROM and an F-ZTATô2 version with on-chip flash memory that can be programmed on-board. These versions enable users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. The F-ZTATô version H8/3048F-ONE includes the on-chip emulator E10T.