HD64F7145F50

Overview

The SH7144 Group and SH7145 Group single-chip RISC (Reduced Instruction Set Computer) microcomputers integrate a Renesas Technology original RISC CPU core with peripheral functions required for system configuration.
The SH7144 Group and SH7145 Group CPU has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microcomputers, such as realtime control, which demands high speeds.

In addition, the SH7144 Group and SH7145 Group includes on-chip peripheral functions necessary for system configuration, such as a direct memory access controller (DMAC), large capacity ROM and RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports. As an option, an I2C bus interface can also be incorporated.

Features

• Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture
⎯ Instruction length: 16-bit fixed length for improved code efficiency
⎯ Load-store architecture (basic operations are executed between registers)
⎯ Sixteen 32-bit general registers
⎯ Five-stage pipeline
⎯ On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) executed in two to four cycles
⎯ C language-oriented 62 basic instructions
• Various peripheral functions
⎯ Direct memory access controller (DMAC)
⎯ Data transfer controller (DTC)
⎯ Multifunction timer/pulse unit (MTU)
⎯ Compare match timer (CMT)
⎯ Watchdog timer (WDT)
⎯ Asynchronous or clocked synchronous serial communication interface (SCI)
⎯ I2C bus interface (IIC)1
⎯ 10-bit A/D converter
⎯ Clock pulse generator
⎯ User break controller (UBC)
⎯ User debugging interface (H-UDI)2
⎯ Advanced user debugger (AUD)*2