CG82NM10 QMJN

Introduction

This document provides specifications for the Intel® NM10 Family Express Chipset, which is designed for use in Intel’s next generation Nettop platform.

Intel® NM10 Family Express Chipset Feature
Support
• Direct Media Interface
— 10 Gb/s each direction, full duplex
— Transparent to software
• PCI Express*
— 4 PCI Express root ports
— Supports PCI Express 1.0a
— Ports 1-4 can be statically configured as 4x1, or 1x4.
— Support for full 2.5 Gb/s bandwidth in each direction per x1 lane
— Module based Hot-Plug supported
• PCI Bus Interface
— Supports PCI Rev 2.3 Specification at 33 MHz
— 2 available PCI REQ/GNT pairs Support for 64-bit addressing on PCI using DAC
protocol
• Integrated Serial ATA Host Controller
— Two ports
— Data transfer rates up to 3.0 Gb/s
(300 MB/s)
— Integrated AHCI controller
• Intel HD Audio Interface
— PCI Express endpoint
— Independent Bus Master logic for eight general purpose streams: four input and
four output
— Support three external Codecs
— Supports variable length stream slots
— Supports multichannel, 32-bit sample depth and 192 kHz sample rate output
— Provides mic array support
— Allows for non-48 kHz sampling output
— Support for ACPI Device States
• SMBus
— Flexible SMBus/SMLink architecture to optimize for ASF
— Provides independent manageability bus through SMLink interface
— Supports SMBus 2.0 Specification
— Host interface allows processor to communicate via SMBus
— Slave interface allows an internal or external Microcontroller to access system
resources
— Compatible with most two-wire components that are also I2C compatible
• High Precision Event Timers
— Advanced operating system interrupt scheduling
• Timers Based on 82C54
— System timer, Refresh request, Speaker tone output
• Real-Time Clock
— 256-byte battery-backed CMOS RAM
— Integrated oscillator components
— Lower Power DC/DC Converter implementation
• System TCO Reduction Circuits
— Timers to generate SMI# and Reset upon detection of system hang
— Timers to detect improper processor reset
— Integrated I/O APIC capability with 24 interrupts
— Supports Processor System Bus interrupt delivery
• 1.05 V operation with 1.5 V and 3.3 V I/O
— 5 V tolerant buffers on PCI, USB and Legacy signals
• 1.05 V Core Voltage
• Integrated 1.05 V Voltage Regulator (INTVR) for the Suspend and LAN wells
Firmware Hub I/F supports BIOS Memory size up to 8 MBytes
• Serial Peripheral Interface (SPI) for Serial and Shared Flash
• Low Pin Count (LPC) I/F
— Supports two Master/DMA devices.
— Support for Security Device (Trusted Platform Module) connected to LPC.
• GPIO
— TTL, Open-Drain, Inversion
• Package 17 mm x17 mm 360 MMAP