ETC5054D

DESCRIPTION

The ETC5057/ETC5054 family consists of A-law and µ–law monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown in the block diagram below, and a serial PCM interface. The devices are fabricated using doublepoly CMOS process. The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto- zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded A-law or µ–law PCM format.

■ COMPLETE CODEC AND FILTERING SYSTEM (DEVICE) INCLUDING:

– Transmit high-pass and low-pass filtering.
– Receive low-pass filter with sin x/x correction.
– Active RC noise filters
– µ-law or A-law compatible COder and DECoder.
– Internal precision voltage reference.
– Serial I/O interface.
– Internal auto-zero circuitry.
■ A-LAW 16 PINS (ETC5057FN, 20 PINS)
■ µ-LAW WITHOUT SIGNALING, 16 PINS (ETC5054FN, 20 PINS)
■ MEETS OR EXCEEDS ALL D3/D4 AND CCITT SPECIFICATIONS
■ ±5V OPERATION
■ LOW OPERATING POWER - TYPICALLY 60 mW
■ POWER-DOWN STANDBY MODE - TYPICALLY 3 mW
■ AUTOMATIC POWER-DOWN
■ TTL OR CMOS COMPATIBLE DIGITAL INTERFACES
■ MAXIMIZES LINE INTERFACE CARD CIRCUIT DENSITY
■ 0 to 70°C OPERATION