MC9S12XDG128CAA

MC9S12XDG128CAA Description

The MC9S12XDG128CAA series is based on the S12 core and has the advantage of low power consumption and high efficiency. It introduces the high performance XGATE module, and the MC9S12XD series is manufactured by NXP. As one of the devices of MC9S12XD series, the 16-bit MC9S12XDG128CAA can be used in PQFP-80 package, which allows CAN, I2C, SCI, SPI and other interface types.

MC9S12XDG128CAA Features

• HCS12X Core
— 16-bit HCS12X CPU
– Upward compatible with MC9S12 instruction set
– Interrupt stacking and programmer’s model identical to MC9S12
– Instruction queue
– Enhanced indexed addressing
– Enhanced instruction set
— EBI (external bus interface)
— MMC (module mapping control)
— INT (interrupt controller)
— DBG (debug module to monitor HCS12X CPU and XGATE bus activity)
— BDM (background debug mode)
• XGATE (peripheral coprocessor)
— Parallel processing module off loads the CPU by providing high-speed data processing and
transfer
— Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports
• PIT (periodic interrupt timer)
— Four timers with independent time-out periods
— Time-out periods selectable between 1 and 224 bus clock cycles
• CRG (clock and reset generator)
— Low noise/low power Pierce oscillator
— PLL
— COP watchdog
— Real time interrupt
— Clock monitor
— Fast wake-up from stop mode
• Port H & Port J with interrupt functionality
— Digital filtering
— Programmable rising or falling edge trigger
• Memory
— 512, 256 and 128-Kbyte Flash EEPROM
— 4 and 2-Kbyte EEPROM
— 32, 16 and 12-Kbyte RAM
• One 16-channel and one 8-channel ADC (analog-to-digital converter）
— 10-bit resolution
— External and internal conversion trigger capabilityFiveFourTwo 1M bit per second,
CAN 2.0 A, B software compatible modules
— Five receive and three transmit buffers
— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit
— Four separate interrupt channels for Rx, Tx, error, and wake-up
— Low-pass filter wake-up function
— Loop-back for self-test operation
• ECT (enhanced capture timer)
— 16-bit main counter with 7-bit prescaler
— 8 programmable input capture or output compare channels
— Four 8-bit or two 16-bit pulse accumulators
• 8 PWM (pulse-width modulator) channels
— Programmable period and duty cycle
— 8-bit 8-channel or 16-bit 4-channel
— Separate control for each pulse width and duty cycle
— Center-aligned or left-aligned outputs
— Programmable clock select logic with a wide range of frequencies
— Fast emergency shutdown input
• Serial interfaces
— SixFourTwo asynchronous serial communication interfaces (SCI) with additional LIN support
and selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width
— ThreeTwo Synchronous Serial Peripheral Interfaces (SPI)
• TwoOne IIC (Inter-IC bus) Modules
— Compatible with IIC bus standard
— Multi-master operation
— Software programmable for one of 256 different serial clock frequencies
• On-Chip Voltage Regulator
— Two parallel, linear voltage regulators with bandgap reference
— Low-voltage detect (LVD) with low-voltage interrupt (LVI)
— Power-on reset (POR) circuit
— 3.3-V–5.5-V operation
— Low-voltage reset (LVR)
— Ultra low-power wake-up timer
• 144-pin LQFP, 112-pin LQFP, and 80-pin QFP packages
— I/O lines with 5-V input and drive capability
— Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation
— 5-V A/D converter inputs
— Operation at 80 MHz equivalent to 40-MHz bus speed
• Development support
— Single-wire background debug™ mode (BDM)
— Four on-chip hardware breakpoints

MC9S12XDG128CAA Applications

• Security and surveillance
• Industrial
• Industrial control
• Home appliances
• Medical devices
• Automotive engine control