HY27UG082G2M-TPCB

SUMMARY DESCRIPTION

Hynix NAND HY27UG088G(5/D)B Series have 1024Mx8bit with spare 32Mx8 bit capacity. The device is offered in 3.3 Vcc Power Supply, and with x8 I/O interface Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.
The device contains 8192 blocks, composed by 64 pages. A program operation allows to write the 2112-byte page in typi cal 200us and an erase operation can be performed in typical 1.5ms on a 128K-byte block. Data in the page can be read out at 25ns cycle time per byte(x8). The I/O pins serve as the ports for address and data input/output as well as command input.
The copy back function allows the optimization of defective blocks management. when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. Copy back operation automatically executes embedded error detection operation: 1 bit error every 528byte (x8) can be detected. Due to this feature, it is no more nor necessary nor recommended to use external 2-bit ECC to detect copy back operation errors. Data read out after copy back read (both for single and multiplane cases) is allowed.
Even the write-intensive systems can take advantage of the HY27UG088G(5/D)B Series extended reliability of 100K pro gram/erase cycles by supporting ECC (Error Correcting Code) with real time mapping-out algorithm. The chip supports CE don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a micro controller, since the CE transitions do not stop the read operation.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension.
The HY27UG088G(5/D)B Series are available in 48-TSOP1 12 x 20 mm, 52-ULGA 12 x 17mm.

FEATURES SUMMARY

HIGH DENSITY NAND FLASH MEMORIES

- Cost effective solutions for mass storage applications

MULTIPLANE ARCHITECTURE

- Array is split into two independent planes. Parallel Operations on both planes are available, halving Program and erase time.

NAND INTERFACE

- x8 bus width.
- Address/ Data Multiplexing
- Pinout compatiblity for all densities

SUPPLY VOLTAGE

- 3.3V device : Vcc = 2.7 V ~3.6 V

MEMORY CELL ARRAY

- x8 : (2K + 64) bytes x 64 pages x 8192 blocks

PAGE SIZE

- (2K + 64 spare) Bytes

BLOCK SIZE

- (128K + 4Kspare) Bytes

PAGE READ / PROGRAM

- Random access : 25us (max.)
- Sequential access : 25ns (min.)
- Page program time : 200us (typ.)
- Multi-page program time (2 pages) : 200us (Typ)

COPY BACK PROGRAM

- Automatic block download without latency time

FAST BLOCK ERASE

- Block erase time: 1.5ms (Typ)
- Multi-block erase time (2 blocks) : 1.5ms (Typ)

STATUS REGISTER

- Normal Status Register (Read/Program/Erase)
- Extended Status Register (EDC)

ELECTRONIC SIGNATURE

- 1st cycle : Manufacturer Code
- 2nd cycle : Device Code
- 3rd cycle : Internal chip number, Cell Type, Number of Simultaneously Programmed Pages.
- 4th cycle : Page size, Block size, Organization, Spare size
- 5th cycle : Multiplane information

CHIP ENABLE DON’T CARE

- Simple interface with microcontroller

HARDWARE DATA PROTECTION

- Program/Erase locked during Power transitions.

DATA RETENTION

- 100,000 Program/Erase cycles (with 1bit/528byte ECC)
- 10 years Data Retention

PACKAGE

- HY27UG088G5B-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27UG088G5B-T (Lead)
- HY27UG088G5B-TP (Lead Free)
- HY27UG088GDB-UP
: 52-ULGA (12 x 17 x 0.65 mm)
- HY27UG088GDB-UP (Lead Free)