MB91F526BWB

DESCRIPTION

The MB91F109 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family) core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU processing for embedded controller applications. To carry out hi-speed performance of CPU instructions, instruction/data Flash memory of 254 Kbytes and RAM of 2 Kbytes + 2 Kbytes are embedded in the MB91F109.

FEATURES
FR CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Operating clock frequency: Internal 25 MHz/external 25 MHz
(PLL used at source oscillation 12.5 MHz)
• General purpose registers: 32 bits × 16
• 16-bit fixed length instructions
(basic instructions), 1 instruction/1 cycle
• Memory to memory transfer, bit processing, barrel shifter processing:
Optimized for embedded applications
• Function entrance/exit instructions, multiple load/store instructions
of register contents, instruction systems
supporting high level languages
• Register interlock functions, efficient assembly language coding
• Branch instructions with delay slots:
Reduced overhead time in branch executions
• Internal multiplier/supported at instruction level
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
• Interrupt (push PC and PS): 6 cycles, 16 priority levels

External bus interface

• Without Clock doubler: Maximum internal bus 25 MHz,
maximum external bus 25 MHz operation
• 25-bit address bus (32 Mbytes memory space)
• 8/16-bit data bus
• Basic external bus cycle: 2 clock cycles
• Chip select outputs for setting down to a
minimum memory block size of 64 Kbytes: 6
• Interface supported for various memory technologies
DRAM interface (area 4 and 5)
• Automatic wait cycle insertion: Flexible setting,
from 0 to 7 for each area
• Unused data/address pins can be configured us input/output ports
• Little endian mode supported (Select 1 area from area 1 to 5)
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